Paul Merolla
According to our database1,
Paul Merolla
authored at least 28 papers
between 2003 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2021
A 1024-Channel Simultaneous Recording Neural SoC with Stimulation and Real-Time Spike Detection.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2016
IEEE Trans. Biomed. Circuits Syst., 2016
Proc. Natl. Acad. Sci. USA, 2016
Deep neural networks are robust to weight binarization and other non-linear distortions.
CoRR, 2016
Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications.
Proceedings of the International Conference for High Performance Computing, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
2015
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the Advances in Neural Information Processing Systems 28: Annual Conference on Neural Information Processing Systems 2015, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations.
Proc. IEEE, 2014
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.
Proceedings of the International Conference for High Performance Computing, 2014
2013
Cognitive computing systems: Algorithms and applications for networks of neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
2012
Building block of a programmable neuromorphic substrate: A digital neurosynaptic core.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
2011
A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
2003
Proceedings of the Advances in Neural Information Processing Systems 16 [Neural Information Processing Systems, 2003