Paul Kwon

According to our database, Paul Kwon authored at least 3 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS.

Zhongkai Wang, Minsoo Choi, Paul Kwon, Zhaokai Liu, Bozhi Yin, Kyoungtae Lee, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2022

Accurate Statistical BER Analysis of DFE Error Propagation in the Presence of Residual ISI.

Kunmo Kim, Paul Kwon, Elad Alon

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology.

Zhongkai Wang, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022