Paul Gao
Affiliations:- University of Washington, Seattle, WA, USA
According to our database1,
Paul Gao
authored at least 8 papers
between 2018 and 2024.
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Bibliography
2024
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
2022
2020
IEEE Micro, 2020
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits, 2020
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020
2019
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
IEEE Micro, 2018