Paul E. R. Lippens

According to our database1, Paul E. R. Lippens authored at least 24 papers between 1990 and 2002.

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Bibliography

2002
C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems.
Des. Autom. Embed. Syst., 2002

2001
Correction to "a two-stage solution approach to multidimensional periodic scheduling".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A two-stage solution approach to multidimensional periodicscheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

HW-SW Co-Design and Verification of a Multi-Standard Video and Image Codec.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

2000
Mapping Array Communication onto FIFO Communication - Towards an Implementation.
Proceedings of the 13th International Symposium on System Synthesis, 2000

1998
The Complexity of Multidimensional Periodic Scheduling.
Discret. Appl. Math., 1998

1997
Multidimensional periodic scheduling: a solution approach.
Proceedings of the European Design and Test Conference, 1997

1996
A video signal processor for motion-compensated field-rate upconversion in consumer television.
IEEE J. Solid State Circuits, 1996

Multidimensional Periodic Scheduling Model and Complexity.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

1995
PHIDEO: High-level synthesis for high throughput applications.
J. VLSI Signal Process., 1995

Improved force-directed scheduling in high-throughput digital signal processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

CAD challenges in multimedia computing.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
Efficient timing constraint derivation for optimal retiming high speed processing units.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Optimization of Address Generator Hardware.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Architectural strategies for high-throughput applications.
J. VLSI Signal Process., 1993

A new method for retiming multi-functional processing units.
Proceedings of the VLSI 93, 1993

Allocation of multiport memories for hierarchical data stream.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Area optimization of multi-functional processing units.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Efficiency improvements for force-directed scheduling.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
Hierarchical Retiming Including Pipelining.
Proceedings of the VLSI 91, 1991

Improved force-directed scheduling.
Proceedings of the conference on European design automation, 1991

PHIDEO: a silicon compiler for high speed algorithms.
Proceedings of the conference on European design automation, 1991

1990
An integrated automatic design system for complex DSP algorithms.
J. VLSI Signal Process., 1990


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