Paul E. Landman

According to our database, Paul E. Landman authored at least 8 papers between 1995 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

15.8 90dB-SFDR 14b 500MS/S BiCMOS switched-current pipelined ADC.

Manar El-Chammas, Xiaopeng Li, Shigenobu Kimura, Jesse Coulon, Jake Hu, David Smith, Paul E. Landman, Mark Weaver

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2005

A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels.

Robert Payne, Paul E. Landman, Bhavesh Bhakta, Sridhar Ramaswamy, Song Wu, John D. Powers, M. Ulvi Erdogan, Ah-Lyan Yee, Richard Gu, Lin Wu, Yiqun Xie, Bharadwaj Parthasarathy, Keith C. Brouse, Wahed Mohammed, Keerthi Heragu, Vikas Gupta, Lisa Dyson, Wai Lee

IEEE J. Solid State Circuits, 2005

1997

A 1-V programmable DSP for wireless communications [CMOS].

Wai Lee, Paul E. Landman, Brock Barton, Shigeshi Abiko, Hiroshi Takahashi, Hiroyuki Mizuno, Shigetoshi Muramatsu, Kenichi Tashiro, Masahiro Fusumada, Luat Pham, Frederic Boutaud, Emmanuel Ego, Girolamo Gallo, Hiep Tran, Carl Lemonds, Albert Shih, Mahalingam Nandakumar, Robert H. Eklund, Ih-Chin Chen

IEEE J. Solid State Circuits, 1997

1996

Activity-sensitive architectural power analysis.

Paul E. Landman, Jan M. Rabaey

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

An Integrated CAD Environment for Low-Power Design.

Paul E. Landman, Renu Mehra, Jan M. Rabaey

IEEE Des. Test Comput., 1996

High-level power estimation.

Paul E. Landman

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995

Architectural power analysis: The dual bit type method.

Paul E. Landman, Jan M. Rabaey

IEEE Trans. Very Large Scale Integr. Syst., 1995

Activity-sensitive architectural power analysis for the control path.

Paul E. Landman, Jan M. Rabaey

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995