Paul Chow

Commun. ACM, August, 2024

The Feasibility of Implementing Large-Scale Transformers on Multi-FPGA Platforms.

[BibT_eX]

[DOI]

Yu Gao

CoRR, 2024

DDC: A Vision for a Disaggregated Datacenter.

[BibT_eX]

[DOI]

Mohammad Ewais

CoRR, 2024

2023

A Lightweight Routing Layer Using a Reliable Link-Layer Protocol.

[BibT_eX]

[DOI]

Qianfeng Shen

CoRR, 2023

Disaggregated Memory in the Datacenter: A Survey.

[BibT_eX]

[DOI]

Mohammad Ewais

IEEE Access, 2023

Partitioning Large-Scale, Multi-FPGA Applications for the Data Center.

[BibT_eX]

[DOI]

Mohammadmahdi Mazraeli

Yu Gao

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

A Lightweight Routing Layer Using a Reliable Link-Layer Protocol.

[BibT_eX]

[DOI]

Qiangfeng Shen

Proceedings of the IEEE International Conference on Cloud Computing Technology and Science, 2023

2022

<i>AIgean</i>: An Open Framework for Deploying Machine Learning on Heterogeneous Clusters.

[BibT_eX]

[DOI]

Naif Tarafdar

Giuseppe Di Guglielmo

ACM Trans. Reconfigurable Technol. Syst., 2022

The Future of FPGA Acceleration in Datacenters and the Cloud.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2022

RIFL: a reliable link layer network protocol for data center communication.

[BibT_eX]

[DOI]

Qianfeng Shen

Jun Zheng

JOCN, 2022

Parallel CRC On An FPGA At Terabit Speeds.

[BibT_eX]

[DOI]

Qianfeng Clark Shen

Proceedings of the International Conference on Field-Programmable Technology, 2022

2021

FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

A PGAS Communication Library for Heterogeneous Clusters.

[BibT_eX]

[DOI]

Varun Sharma

CoRR, 2021

A Framework Integrating FPGAs in VNF Networks.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Network of the Future, 2021

Pharos: a Multi-FPGA Performance Monitor.

[BibT_eX]

[DOI]

Arzhang Rafii

Welson Sun

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPGA Communication.

[BibT_eX]

[DOI]

Qianfeng Clark Shen

Jun Zheng

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Exploring PGAS Communication for Heterogeneous Clusters with FPGAs.

[BibT_eX]

[DOI]

Varun Sharma

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Interactive Debugging at IP Block Interfaces in FPGAs.

[BibT_eX]

[DOI]

Marco Antonio Merlini

Isamu Poy

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

FFIVE: An FPGA Framework for Interactive VNF Environments.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Pharos: a Performance Monitor for Multi-FPGA Systems.

[BibT_eX]

[DOI]

Arzhang Rafii

Welson Sun

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020

SHIP: Storage for Hybrid Interconnected Processors.

[BibT_eX]

[DOI]

Qianfeng Clark Shen

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark.

[BibT_eX]

[DOI]

Marco Antonio Merlini

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

AIgean: An Open Framework for Machine Learning on Heterogeneous Clusters.

[BibT_eX]

[DOI]

Naif Tarafdar

Giuseppe Di Guglielmo

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Hierarchical Modelling of Generators in Design-Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

Accelerating Apache Spark with FPGAs.

[BibT_eX]

[DOI]

Ehsan Ghasemi

Concurr. Comput. Pract. Exp., 2019

Introducing ReCPRI: A Field Re-configurable Protocol for Backhaul Communication in a Radio Access Network.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Symposium on Integrated Network Management, 2019

The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs.

[BibT_eX]

[DOI]

Daniel Rozhko

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Sonar: Writing Testbenches through Python.

[BibT_eX]

[DOI]

Varun Sharma

Naif Tarafdar

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018

Galapagos: A Full Stack Approach to FPGA Integration in the Cloud.

[BibT_eX]

[DOI]

IEEE Micro, 2018

Designing for FPGAs in the Cloud.

[BibT_eX]

[DOI]

IEEE Des. Test, 2018

HLS-based FPGA Acceleration of Light Propagation Simulation in Turbid Media.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

Multi-fidelity Optimization for High-Level Synthesis Directives.

[BibT_eX]

[DOI]

Fernando Martin del Campo

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Task replication and control for highly parallel in-memory stores.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2017

Enabling FPGAs as a True Device in the OpenCL Standard: Bridging the Gap for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 5th International Workshop on OpenCL, 2017

An FPGA-based processor for training convolutional neural networks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2017

FPGA-based training of convolutional neural networks with a reduced precision floating-point library.

[BibT_eX]

[DOI]

Roberto DiCecco

Lin Sun

Proceedings of the International Conference on Field Programmable Technology, 2017

Heterogeneous virtualized network function framework for the data center.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Building the Reconfigurable Cloud Ecosystem.

[BibT_eX]

[DOI]

Proceedings of the first Workshop on Emerging Technologies for software-defined and reconfigurable hardware-accelerated Cloud Datacenters, 2017

Enabling network function virtualization over heterogeneous resources.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia-Pacific Network Operations and Management Symposium, 2017

2016

CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2016

Extracting Designs of Secure IPs Using FPGA CAD Tools.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Model-based optimization of High Level Synthesis directives.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only).

[BibT_eX]

[DOI]

Ehsan Ghasemi

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Accelerating Apache Spark Big Data Analysis with FPGAs.

[BibT_eX]

[DOI]

Ehsan Ghasemi

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015

An Enhanced Adaptive Recoding Rotation CORDIC.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs.

[BibT_eX]

[DOI]

Fernando Martin del Campo

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Architecture Exploration for Data Intensive Applications.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Symposium on Memory Systems, 2015

FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC.

[BibT_eX]

[DOI]

Fernando Martinez-Vallina

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

OpenCL library of stream memory components targeting FPGAs.

[BibT_eX]

[DOI]

Henry Styles

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Exploring pipe implementations using an OpenCL framework for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware.

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014

Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications.

[BibT_eX]

[DOI]

Yuanxi Peng

Xiaofeng Zou

ACM Trans. Reconfigurable Technol. Syst., 2014

A Software Parallel Programming Approach to FPGA-Accelerated Computing.

[BibT_eX]

[DOI]

CoRR, 2014

Virtualized Reconfigurable Hardware Resources in the SAVI Testbed.

[BibT_eX]

[DOI]

Proceedings of the Testbeds and Research Infrastructure: Development of Networks and Communities, 2014

A Heterogeneous GASNet Implementation for FPGA-accelerated Computing.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Partitioned Global Address Space Programming Models, 2014

An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use.

[BibT_eX]

[DOI]

Jasmina Vasiljevic

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Using an OpenCL framework to evaluate interconnect implementations on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

MPack: global memory optimization for stream applications in high-level synthesis.

[BibT_eX]

[DOI]

Jasmina Vasiljevic

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013

ZCluster: A Zynq-based Hadoop cluster.

[BibT_eX]

[DOI]

Zhongduo Lin

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Why Put FPGAs in your CPU socket?

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

SimXMD: Simulation-based HW/SW co-debugging.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Simulation-based HW/SW co-debugging for field-programmable systems-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract.

[BibT_eX]

[DOI]

Stuart Byma

J. Gregory Steffan

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A remote memory access infrastructure for global address space programming models in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012

Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2012

An implementation of a directory protocol for a cache coherent system on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

SimXMD: Integrated debugging of C code and hardware components.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Managing mutex variables in a cache-coherent shared-memory system for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

A high-performance architecture for training Viola-Jones object detectors.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

K-means implementation on FPGA for high-dimensional data using triangle inequality.

[BibT_eX]

[DOI]

Zhongduo Lin

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

FCache: a system for cache coherent processing on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

OpenCL memory infrastructure for FPGAs (abstract only).

[BibT_eX]

[DOI]

S. Alexander Chin

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011

Leveraging reconfigurability in the hardware/software codesign process.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2011

FPGA Acceleration of MultiFactor CDO Pricing.

[BibT_eX]

[DOI]

Alexander Kaganov

Asif Lakhany

ACM Trans. Reconfigurable Technol. Syst., 2011

Hardware Support for Broadcast and Reduce in MPSoC.

[BibT_eX]

[DOI]

Yuanxi Peng

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010

MPI as a Programming Model for High-Performance Reconfigurable Computers.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2010

High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 2010

Virtualized Application Networking Infrastructure.

[BibT_eX]

[DOI]

Proceedings of the Testbeds and Research Infrastructures. Development of Networks and Communities, 2010

Using Partial Reconfiguration in an Embedded Message-Passing System.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Acceleration of an analytical approach to collateralized debt obligation pricing.

[BibT_eX]

[DOI]

Dharmendra P. Gupta

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Integrating High-Level Synthesis into MPI.

[BibT_eX]

[DOI]

Andrew W. H. House

Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2009

A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems.

[BibT_eX]

[DOI]

Emanuel Ramalho

Int. J. Reconfigurable Comput., 2009

Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Programming the Nallatech Xeon + multi-FPGA heterogeneous platform.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE Hot Chips 21 Symposium (HCS), 2009

The challenges of using an embedded MPI for hardware-based processing nodes.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

A multi-FPGA architecture for stochastic Restricted Boltzmann Machines.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A high-performance FPGA architecture for restricted boltzmann machines.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy.

[BibT_eX]

[DOI]

Proceedings of the FCCM 2009, 2009

2008

Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy.

[BibT_eX]

[DOI]

Tor M. Aamodt

ACM Trans. Embed. Comput. Syst., 2008

MPI as an abstraction for software-hardware interaction for HPRCs.

[BibT_eX]

[DOI]

Proceedings of the 2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications, 2008

A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI.

[BibT_eX]

[DOI]

Emanuel Ramalho

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

A profiler for a heterogeneous multi-core multi-FPGA system.

[BibT_eX]

[DOI]

Daniel Nunes

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

FPGA acceleration of Monte-Carlo based credit derivative pricing.

[BibT_eX]

[DOI]

Alexander Kaganov

Asif Lakhany

Proceedings of the FPL 2008, 2008

Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems.

[BibT_eX]

[DOI]

Andrew W. H. House

Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2007

SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Routability of Network Topologies in FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Optimization of data prefetch helper threads with path-expression based statistical modeling.

[BibT_eX]

[DOI]

Tor M. Aamodt

Proceedings of the 21th Annual International Conference on Supercomputing, 2007

Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor.

[BibT_eX]

[DOI]

Chichyang Chen

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Integrating FPGAs in high-performance computing: introduction.

[BibT_eX]

[DOI]

Mike Hutton

Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

An FPGA Implementation of Reciprocal Sums for SPME.

[BibT_eX]

Sam Lee

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

A CMOS Image Sensor for DNA Microarrays.

[BibT_eX]

[DOI]

Samir Parikh

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

The routability of multiprocessor network topologies in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

A Scalable FPGA-based Multiprocessor.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005

Designing an FPGA SoC Using a Standardized IP Block Interface.

[BibT_eX]

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Leveraging Reconfigurability in the Design Process.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004

Hardware Support for Prescient Instruction Prefetch.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

Maximizing system performance: using reconfigurability to monitor system communications.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Using reconfigurability to achieve real-time profiling for hardware/software codesign.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

FPGA-based supercomputing: an implementation for molecular dynamics.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Reconfigurable Molecular Dynamics Simulator.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003

A framework for modeling and optimization of prescient instruction prefetch.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2003

Standardizing the Performance Assessment of Reconfigurable Processor Architectures.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

2001

The effect of reconfigurable units in superscalar processors.

[BibT_eX]

[DOI]

Jorge E. Carrillo

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

2000

A Scheduler ASIC for a Programmable Packet Switch.

[BibT_eX]

[DOI]

IEEE Micro, 2000

Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation.

[BibT_eX]

[DOI]

Tor M. Aamodt

Proceedings of the 2000 International Conference on Compilers, 2000

1999

The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

The design of an SRAM-based field-programmable gate array. I. Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 1999

Memory Interfacing and Instruction Specification for Reconfigurable Processors.

[BibT_eX]

[DOI]

Jeffrey A. Jacob

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

DES Cracking on the Transmogrifier 2a.

[BibT_eX]

[DOI]

Ivan Hamer

Proceedings of the Cryptographic Hardware and Embedded Systems, 1999

1998

The Transmogrifier-2: a 1 million gate rapid-prototyping system.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

1997

The Multicluster Architecture: Reducing Cycle Time Through Partitioning.

[BibT_eX]

[DOI]

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Memory-System Design Considerations for Dynamically-Scheduled Processors.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Computer Architecture, 1997

1996

[BibT_eX]

[DOI]

Keith I. Farkas

Norman P. Jouppi

Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996

RACER: a reconfigurable constraint-length 14 Viterbi decoder.

[BibT_eX]

[DOI]

David Yeh

Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

OneChip: an FPGA processor with reconfigurable logic.

[BibT_eX]

[DOI]

Ralph Wittig

Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

Exploiting Dual Data-Memory Banks in Digital Signal Processors.

[BibT_eX]

[DOI]

Mazen A. R. Saghir

Corinna G. Lee

Proceedings of the ASPLOS-VII Proceedings, 1996

1995

How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?

[BibT_eX]

[DOI]

Keith I. Farkas

Norman P. Jouppi

Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

A Field-Programmable Mixed-Analog-Digital Array.

[BibT_eX]

[DOI]

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994

Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding.

[BibT_eX]

[DOI]

Inf. Process. Manag., 1994

Application-driven design of DSP architectures and compilers.

[BibT_eX]

[DOI]

Mazen A. R. Saghir

Corinna G. Lee

Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression.

[BibT_eX]

[DOI]

Proceedings of the IEEE Data Compression Conference, 1994

1993

A multiprocessor architecture for Viterbi decoders with linear speedup.

[BibT_eX]

[DOI]

Patrick Glenn Gulak

IEEE Trans. Signal Process., 1993

A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Data Compression Conference, 1993

1991

A streamlined DSP microprocessor architecture.

[BibT_eX]

[DOI]

Michael Takefman

Proceedings of the 1991 International Conference on Acoustics, 1991

Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up.

[BibT_eX]

[DOI]

Patrick Glenn Gulak

Proceedings of the 1991 International Conference on Acoustics, 1991

1990

Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, October, 1990

1987

Architectural Tradeoffs in the Design of MIPS-X.

[BibT_eX]

[DOI]

Mark Horowitz

Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987

1983

A Pipelined Distributed Arithmetic PFFT Processor.

[BibT_eX]

[DOI]