Paul C. Parries

According to our database, Paul C. Parries authored at least 10 papers between 2005 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Process technology for IBM 14-nm processor designs featuring silicon-on-insulator FinFETs.

Scott R. Stiffler, Ravikumar Ramachandran, W. Kirklen Henson, Noah Zamdmer, Kevin McStay, Giuseppe La Rosa, Kevin M. Boyd, Sungjae Lee, Claude Ortolland, Paul C. Parries

IBM J. Res. Dev., 2018

2015

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM.

Gregory Freeman, Paul Chang, E. R. Engbrecht, K. J. Giewont, David F. Hilscher, M. Lagus, Timothy J. McArdle, B. Morgenfeld, Shreesh Narasimha, James P. Norum, K. A. Nummy, Paul C. Parries, G. Wang, Jonathan K. Winslow, Paul D. Agnello, Rajeev Malik

IBM J. Res. Dev., 2015

2012

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond.

Balaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications.

Subramanian S. Iyer, Greg G. Freeman, Colin Brodsky, Anthony I. Chou, Dan Corliss, Sameer H. Jain, Naftali E. Lustig, Vincent McGahay, Shreesh Narasimha, James P. Norum, Karen A. Nummy, Paul C. Parries, Sujatha Sankaran, Chris D. Sheraw, Pushkara Rao Varanasi, Geng Wang, Mary E. Weybright, Xiaojun Yu, Emmanuel Crabbe, Paul D. Agnello

IBM J. Res. Dev., 2011

2009

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2009

2008

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.

John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2008

Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation.

Wei Kong, Paul C. Parries, G. Wang, Subramanian S. Iyer

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.

John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

An 800-MHz embedded DRAM with a concurrent refresh mode.

Toshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2005

Embedded DRAM: Technology platform for the Blue Gene/L chip.

Subramanian S. Iyer, John E. Barth Jr., Paul C. Parries, James P. Norum, James P. Rice, Lyndon R. Logan, Dennis Hoyniak

IBM J. Res. Dev., 2005