Paul Bunce

According to our database, Paul Bunce authored at least 5 papers between 1992 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor.

John Davis, Paul Bunce, Diana M. Henderson, Yuen H. Chan, Uma Srinivasan, Daniel Rodko, Pradip Patel, Thomas J. Knips, Tobias Werner

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System.

James D. Warnock, Yiu-Hing Chan, Sean M. Carey, Huajun Wen, Patrick J. Meaney, Guenter Gerwig, Howard H. Smith, Yuen H. Chan, John Davis, Paul Bunce, Antonio Pelella, Daniel Rodko, Pradip Patel, Thomas Strach, Doug Malone, Frank Malgioglio, José Neves, David L. Rude, William V. Huott

IEEE J. Solid State Circuits, 2012

2006

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor.

John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2000

Design validation of .18 μm 1 GHz cache and register arrays.

Doug Malone, Paul Bunce, Joe DellaPietro, John Davis, James Dawson, Thomas J. Knips, Don Plass, Phil Pritzlaff, Kenneth Reyer

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1992

Directory and Trace memory chip with active discharge cell.

Paul Bunce, William Chin, Leo Clark, Barry Krumm

IBM J. Res. Dev., 1992