Paul Ampadu
Orcid: 0000-0002-8547-308X
According to our database1,
Paul Ampadu
authored at least 76 papers
between 2006 and 2025.
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Bibliography
2025
A Fast Transient Response Distributed Power Supply With Dynamic Output Switching for Power Side-Channel Attack Mitigation.
IEEE Trans. Very Large Scale Integr. Syst., January, 2025
2022
Efficient Low-bit-width Activation Function Implementations for Ultra Low Power SoCs.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
A Scalable DC/DC Converter with Fast Load Transient Response and Security Improvement.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
A Scalable Integrated DC/DC Converter with Enhanced Load Transient Response and Security for Emerging SoC Applications.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A Scalable Single-Input-Multiple-Output DC/DC Converter with Enhanced Load Transient Response and Security for Low-Power SoCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
J. Cryptogr. Eng., 2021
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
2020
IEEE Trans. Computers, 2020
SCARL: Side-Channel Analysis with Reinforcement Learning on the Ascon Authenticated Cipher.
CoRR, 2020
RS-Mask: Random Space Masking as an Integrated Countermeasure against Power and Fault Analysis.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020
2019
Energy-efficient and high-performance NoC architecture and mapping solution for deep neural networks.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
A Novel Single-Input-Multiple-Output DC/DC Converter for Distributed Power Management in Many-Core Systems.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Approximate Communication Strategies for Energy-Efficient and High Performance NoC: Opportunities and Challenges.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2019
2018
An Energy-Efficient NoC Router with Adaptive Fault-Tolerance Using Channel Slicing and On-Demand TMR.
IEEE Trans. Emerg. Top. Comput., 2018
Reconfigurable Clock Generator with Wide Frequency Range and Single-Cycle Phase and Frequency Switching.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
2017
Proceedings of the 10th International Workshop on Network on Chip Architectures, 2017
2016
Proceedings of the 9th International Workshop on Network on Chip Architectures, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
2013
Addressing network-on-chip router transient errors with inherent information redundancy.
ACM Trans. Embed. Comput. Syst., 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Exploiting Programmable Temperature Compensation Devices to Manage Temperature-Induced Delay Uncertainty.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 International Green Computing Conference, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Proceedings of the NOCS 2011, 2011
Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration.
Proceedings of the NOCS 2011, 2011
Proceedings of the Low Power Networks-on-Chip., 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects.
IET Comput. Digit. Tech., 2010
Proceedings of the NOCS 2010, 2010
Proceedings of the NOCS 2010, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
J. Signal Process. Syst., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
ACM J. Emerg. Technol. Comput. Syst., 2009
IET Comput. Digit. Tech., 2009
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
An Energy-Efficient Multiwire Error Control Scheme for Reliable On-Chip Interconnects Using Hamming Product Codes.
VLSI Design, 2008
J. Circuits Syst. Comput., 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
A multi-wire error correction scheme for reliable and energy efficient SOC links using hamming product codes.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates.
Proceedings of the Nano-Net - Third International ICST Conference, 2008
Proceedings of the Nano-Net - Third International ICST Conference, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
2007
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006