Patsy Cadareanu
According to our database1,
Patsy Cadareanu
authored at least 7 papers
between 2018 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
2018
2019
2020
2021
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Bibliography
2021
A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Proceedings of the International Conference on Computer-Aided Design, 2018