Patrick Vuillod

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

LUT-Based Optimization For ASIC Design Flow.

[BibT_eX]

[DOI]

Luca Gaetano Amarù

Vinicius N. Possani

Eleonora Testa

Felipe S. Marranghello

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Extending Boolean Methods for Scalable Logic Synthesis.

[BibT_eX]

[DOI]

IEEE Access, 2020

SAT-Sweeping Enhanced for Logic Synthesis.

[BibT_eX]

[DOI]

Luca G. Amarù

Felipe S. Marranghello

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Scalable Boolean Methods in a Modern Synthesis Flow.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Integrated ESOP Refactoring for Industrial Designs.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Improvements to boolean resynthesis.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Enabling exact delay synthesis.

[BibT_eX]

[DOI]

Janet Olson

Robert K. Brayton

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Logic optimization and synthesis: Trends and directions in industry.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Multi-level logic benchmarks: An exactness study.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

1998

Iterative remapping for logic circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997

Clock Skew Optimization for Peak Current Reduction.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1997

Re-mapping for low power under tight timing constraints.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Generalized matching from theory to application.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification.

[BibT_eX]

[DOI]

Claudionor José Nunes Coelho Jr.