Patrick Stolt

According to our database, Patrick Stolt authored at least 3 papers between 2015 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Probabilistic replacement strategies for improving the lifetimes of NVM-based caches.

Elizabeth Reed, Alaa R. Alameldeen, Helia Naeimi, Patrick Stolt

Proceedings of the International Symposium on Memory Systems, 2017

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache.

Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima, Patrick Stolt, Shih-Lien Lu

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.

Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu

Proceedings of the Symposium on VLSI Circuits, 2015