Patrick Sittel

Orcid: 0000-0003-2896-3709

According to our database1, Patrick Sittel authored at least 12 papers between 2017 and 2022.

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Bibliography

2022
Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2020
Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling.
Proceedings of the Euro-Par 2019: Parallel Processing, 2019

2018
ScaLP: A Light-Weighted (MI)LP-Library.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2018

Constant Matrix Multiplication with Ternary Adders.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

ILP-Based Modulo Scheduling and Binding for Register Minimization.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

Model-based hardware design based on compatible sets of isomorphic subgraphs.
Proceedings of the International Conference on Field Programmable Technology, 2017


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