Patrick Schaumont
Orcid: 0000-0002-4586-5476Affiliations:
- Worcester Polytechnic University, MA, USA
- Virginia Tech, Blacksburg, Department of Electrical and Computer Engineering (former)
According to our database1,
Patrick Schaumont
authored at least 256 papers
between 1997 and 2024.
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Bibliography
2024
Analysis of EM Fault Injection on Bit-sliced Number Theoretic Transform Software in Dilithium.
ACM Trans. Embed. Comput. Syst., March, 2024
IEEE Trans. Emerg. Top. Comput., 2024
Guest Editorial IEEE Transactions on Emerging Topics in Computing Special Section on Advances in Emerging Privacy-Preserving Computing.
IEEE Trans. Emerg. Top. Comput., 2024
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024
IACR Cryptol. ePrint Arch., 2024
T-Scope: Side-channel Leakage Assessment with a Hardware-accelerated Online TVLA Test.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2023
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2023
2022
ACM Trans. Embed. Comput. Syst., 2022
SoC Root Canal! Root Cause Analysis of Power Side-Channel Leakage in System-on-Chip Designs.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
ScatterVerif: Verification of Electronic Boards Using Reflection Response of Power Distribution Network.
ACM J. Emerg. Technol. Comput. Syst., 2022
IEEE Internet Things J., 2022
CoRR, 2022
CoRR, 2022
Computer, 2022
Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the 7th IEEE European Symposium on Security and Privacy, 2022
2021
Pre-silicon Architecture Correlation Analysis (PACA): Identifying and Mitigating the Source of Side-channel Leakage at Gate-level.
IACR Cryptol. ePrint Arch., 2021
Programmable RO (PRO): A Multipurpose Countermeasure against Side-channel and Fault Injection Attacks.
IACR Cryptol. ePrint Arch., 2021
IACR Cryptol. ePrint Arch., 2021
IACR Cryptol. ePrint Arch., 2021
Dimming Down LED: An Open-source Threshold Implementation on Light Encryption Device (LED) Block Cipher.
CoRR, 2021
Real-time Detection and Adaptive Mitigation of Power-based Side-Channel Leakage in SoC.
CoRR, 2021
Programmable RO (PRO): A Multipurpose Countermeasure against Side-channel and Fault Injection Attack.
CoRR, 2021
Security for Emerging Miniaturized Wireless Biomedical Devices: Threat Modeling with Application to Case Studies.
CoRR, 2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Rewrite to Reinforce: Rewriting the Binary to Apply Countermeasures against Fault Injection.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
J. Hardw. Syst. Secur., 2020
Architecture Correlation Analysis (ACA): Identifying the Source of Side-channel Leakage at Gate-level.
IACR Cryptol. ePrint Arch., 2020
IACR Cryptol. ePrint Arch., 2020
IACR Cryptol. ePrint Arch., 2020
Custom Instruction Support for Modular Defense against Side-channel and Fault Attacks.
IACR Cryptol. ePrint Arch., 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Minimum On-the-node Data Security for the Next-generation Miniaturized Wireless Biomedical Devices.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the 25th International Conference on Pattern Recognition, 2020
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020
Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the CCS '20: 2020 ACM SIGSAC Conference on Computer and Communications Security, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Dependable Secur. Comput., 2019
IACR Cryptol. ePrint Arch., 2019
Dagstuhl Reports, 2019
SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, 2019
2018
J. Hardw. Syst. Secur., 2018
IEEE Des. Test, 2018
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2018
Proceedings of the 27th ACM SIGSOFT International Symposium on Software Testing and Analysis, 2018
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
A Low-cost Function Call Protection Mechanism Against Instruction Skip Fault Attacks.
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018
2017
ACM Trans. Embed. Comput. Syst., 2017
IEEE Trans. Computers, 2017
Security by compilation: an automated approach to comprehensive side-channel resistance.
ACM SIGLOG News, 2017
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security, 2017
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
IEEE Trans. Computers, 2016
Sustain. Comput. Informatics Syst., 2016
Compact and low-power ASIP design for lightweight PUF-based authentication protocols.
IET Inf. Secur., 2016
IACR Cryptol. ePrint Arch., 2016
IEEE Embed. Syst. Lett., 2016
Keymill: Side-Channel Resilient Key Generator, A New Concept for SCA-Security by Design - A New Concept for SCA-Security by Design.
Proceedings of the Selected Areas in Cryptography - SAC 2016, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
FAME: Fault-attack Aware Microprocessor Extensions for Hardware Fault Detection and Software Fault Response.
Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016
SIMD Instruction Set Extensions for Keccak with Applications to SHA-3, Keyak and Ketje.
Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016
Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
IEEE Trans. Inf. Forensics Secur., 2015
ACM Trans. Embed. Comput. Syst., 2015
The Future of Real-Time Security: Latency-Optimized Lattice-Based Digital Signatures.
ACM Trans. Embed. Comput. Syst., 2015
Quantitative Masking Strength: Quantifying the Power Side-Channel Resistance of Software Code.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Hardware/software co-design of physical unclonable function based authentications on FPGAs.
Microprocess. Microsystems, 2015
IACR Cryptol. ePrint Arch., 2015
Precomputation Methods for Faster and Greener Post-Quantum Cryptography on Emerging Embedded Platforms.
IACR Cryptol. ePrint Arch., 2015
IACR Cryptol. ePrint Arch., 2015
Proceedings of the Progress in Cryptology - INDOCRYPT 2015, 2015
TVVF: Estimating the vulnerability of hardware cryptosystems against timing violation attacks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
Proceedings of the 2015 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2015
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
ACM Trans. Softw. Eng. Methodol., 2014
NII Shonan Meet. Rep., 2014
IACR Cryptol. ePrint Arch., 2014
IEEE Embed. Syst. Lett., 2014
Proceedings of the IEEE Wireless Communications and Networking Conference, 2014
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2014
Energy Budget Analysis for Signature Protocols on a Self-powered Wireless Sensor Node.
Proceedings of the Radio Frequency Identification: Security and Privacy Issues, 2014
Proceedings of the Lightweight Cryptography for Security and Privacy, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Proceedings of the IEEE Global Communications Conference, 2014
Proceedings of the 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2014
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
IEEE Trans. Computers, 2013
Microprocess. Microsystems, 2013
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2013
Proceedings of the Radio Frequency Identification, 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013
Proceedings of the Advances in Information and Computer Security, 2013
Proceedings of the IEEE High Performance Extreme Computing Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013
Study of ASIC technology impact factors on performance evaluation of SHA-3 candidates.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the Workshop on Embedded Systems Security, 2013
2012
IEEE Trans. Inf. Forensics Secur., 2012
Int. J. Reconfigurable Comput., 2012
Simulating power/energy consumption of sensor nodes with flexible hardware in wireless networks.
Proceedings of the 9th Annual IEEE Communications Society Conference on Sensor, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Efficient and side-channel-secure block cipher implementation with custom instructions on FPGA.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
A Parallel Implementation of Montgomery Multiplication on Multicore Systems: Algorithm, Analysis, and Prototype.
IEEE Trans. Computers, 2011
A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions.
IACR Cryptol. ePrint Arch., 2011
SUNSHINE extension: a hardware-software emulator for flexible sensor nodes in wireless networks.
Proceedings of the 9th International Conference on Embedded Networked Sensor Systems, 2011
Proceedings of the 8th Annual IEEE Communications Society Conference on Sensor, 2011
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
An Integrated Prime-Field ECDLP Hardware Accelerator with High-Performance Modular Arithmetic Units.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the Seventh International Conference on Mobile Ad-hoc and Sensor Networks, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Data-oriented performance analysis of SHA-3 candidates on FPGA accelerated computers.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the Towards Hardware-Intrinsic Security - Foundations and Practice, 2010
ACM Trans. Reconfigurable Technol. Syst., 2010
IEEE Trans. Ind. Informatics, 2010
ACM SIGMOBILE Mob. Comput. Commun. Rev., 2010
IACR Cryptol. ePrint Arch., 2010
Virtual Secure Circuit: Porting Dual-Rail Pre-charge Technique into Software on Multicore.
IACR Cryptol. ePrint Arch., 2010
State-of-the-art of Secure ECC Implementations: A Survey on Known Side-channel Attacks and Countermeasures.
Proceedings of the HOST 2010, 2010
pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systems.
Proceedings of the Design, Automation and Test in Europe, 2010
A comprehensive analysis of performance and side-channel-leakage of AES SBOX implementations in embedded software.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010
Proceedings of the 2010 International Conference on Compilers, 2010
Proceedings of the Reconfigurable Computing: Architectures, 2010
Proceedings of the Secure Integrated Circuits and Systems, 2010
Springer, ISBN: 978-1-4419-5999-7, 2010
2009
ACM Trans. Reconfigurable Technol. Syst., 2009
IACR Cryptol. ePrint Arch., 2009
Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009
Proceedings of the Advances in Information Security and Assurance, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
Extended Abstract: Early Feedback on Side-Channel Risks with Accelerated Toggle-Counting.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009
Physical unclonable function and true random number generator: a compact and scalable implementation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Impact and compensation of correlated process variation on ring oscillator based puf.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009
Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Foundations for Forgery-Resilient Cryptographic Hardware, 05.07., 2009
Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform.
Proceedings of the Reconfigurable Computing: Architectures, 2009
2008
Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors.
Proceedings of the Embedded Computer Systems: Architectures, 2008
Proceedings of the Embedded Computer Systems: Architectures, 2008
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008
Turning liabilities into assets: Exploiting deep submicron CMOS technology to design secure embedded circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008
2007
IEEE Des. Test Comput., 2007
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007
2006
ACM Trans. Design Autom. Electr. Syst., 2006
IEEE Trans. Computers, 2006
AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks.
IEEE J. Solid State Circuits, 2006
Proceedings of the Selected Areas in Cryptography, 13th International Workshop, 2006
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Process Isolation for Reconfigurable Hardware.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Int. J. Embed. Syst., 2005
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005
Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip.
Proceedings of the 2005 Design, 2005
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing.
Proceedings of the 42nd Design Automation Conference, 2005
Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design.
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005
2004
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
The happy marriage of architecture and application in next-generation reconfigurable systems.
Proceedings of the First Conference on Computing Frontiers, 2004
Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques.
Proceedings of the 2004 International Conference on Compilers, 2004
Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing.
Proceedings of the Ultra Low-Power Electronics and Design, 2004
2003
IEEE J. Solid State Circuits, 2003
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system.
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.
J. Supercomput., 2002
Des. Autom. Embed. Syst., 2002
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 μm CMOS technology.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
A Security Protocol for Biometric Smart Cards.
Proceedings of the Fifth Smart Card Research and Advanced Application Conference, 2002
2001
IEEE J. Solid State Circuits, 2001
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware.
Proceedings of the Field-Programmable Logic and Applications, 2001
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
Proceedings of ASP-DAC 2001, 2001
2000
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000
Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000
Functional verification of an embedded network component by co-simulation with a real network.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000
Standards for System-Level Design: Practical Reality or Solution in Search of a Question?
Proceedings of the 2000 Design, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 1999 Design, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998
Proceedings of the 35th Conference on Design Automation, 1998
1997
IEEE Trans. Very Large Scale Integr. Syst., 1997
Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination.
Proceedings of the 10th International Symposium on System Synthesis, 1997
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications.
Proceedings of the European Design and Test Conference, 1997