Pathik Viramgama

According to our database, Pathik Viramgama authored at least 1 paper in 2017.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2017

Characterization of a Novel 10T Low-Voltage SRAM Cell with High Read and Write Margin for 20nm FinFET Technology.

Mitesh Limachia, Pathik Viramgama, Rajesh Amratlal Thakker, Nikhil Kothari

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017