Pasquale Davide Schiavone
Orcid: 0000-0003-2931-0435
According to our database1,
Pasquale Davide Schiavone
authored at least 24 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
CoRR, 2024
CoRR, 2024
BiomedBench: A benchmark suite of TinyML biomedical applications for low-power wearables.
CoRR, 2024
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators.
CoRR, 2024
Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024
2023
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
2022
Motor-Unit Ordering of Blindly-Separated Surface-EMG Signals for Gesture Recognition.
Proceedings of the Advances in System-Integrated Intelligence, 2022
sEMG Neural Spikes Reconstruction for Gesture Recognition on a Low-Power Multicore Processor.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Always-On 674μ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node.
IEEE Trans. Circuits Syst., 2020
Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node.
CoRR, 2020
Neuro-PULP: A Paradigm Shift Towards Fully Programmable Platforms for Neural Interfaces.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
2018
XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
A sensor fusion approach for drowsiness detection in wearable ultra-low-power systems.
Inf. Fusion, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Fast and Accurate Multiclass Inference for MI-BCIs Using Large Multiscale Temporal and Spectral Features.
Proceedings of the 26th European Signal Processing Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
2015
Proceedings of the 16th Latin-American Test Symposium, 2015