Pascal Vivet
Orcid: 0000-0002-7413-8243Affiliations:
- CEA-LETI, Grenoble, France
According to our database1,
Pascal Vivet
authored at least 100 papers
between 1998 and 2023.
Collaborative distances:
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Bibliography
2023
The CNN vs. SNN Event-camera Dichotomy and Perspectives For Event-Graph Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
HUGNet: Hemi-Spherical Update Graph Neural Network applied to low-latency event-based optical flow.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
Proceedings of the 34th British Machine Vision Conference 2023, 2023
2022
ACM Trans. Archit. Code Optim., 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.
IEEE J. Solid State Circuits, 2021
2020
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning.
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019
Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2018
Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
BISTs for post-bond test and electrical analysis of high density 3D interconnect defects.
Proceedings of the 23rd IEEE European Test Symposium, 2018
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2017
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
IEEE J. Solid State Circuits, 2017
Innovative structures to test bonding alignment and characterize high density interconnects in 3D-IC.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
2016
Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Des. Test, 2016
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system.
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2015
Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
A simulation framework for rapid prototyping and evaluation of thermal mitigation techniques in many-core architectures.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC.
IEEE J. Solid State Circuits, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Thermal impact of 3D stacking and die thickness: Analysis and characterization of a memory-on-logic 3D circuit.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Early design stage thermal evaluation and mitigation: The locomotiv architectural case.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators.
Proceedings of the 2014 International Conference on Compilers, 2014
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Fast and accurate power annotated simulation: Application to a many-core architecture.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC.
Proceedings of the ESSCIRC 2013, 2013
Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools.
Proceedings of the Design, Automation and Test in Europe, 2013
Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications.
Proceedings of the Design, Automation and Test in Europe, 2013
A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
An accurate Single Event Effect digital design flow for reliable system level design.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
2011
On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling.
J. Low Power Electron., 2011
Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures.
J. Low Power Electron., 2011
Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems.
IEEE Des. Test Comput., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
2010
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Bringing Robustness and Power Efficiency to Autonomous Energy Harvesting Microsystems.
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE J. Solid State Circuits, 2009
A Communication and configuration controller for NoC based reconfigurable data flow architecture.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
2008
IEEE J. Solid State Circuits, 2008
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs.
Proceedings of the ESSCIRC 2008, 2008
Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008
2007
IEEE Des. Test Comput., 2007
Proceedings of the 2007 IEEE International Conference on Research, 2007
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC.
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007
2006
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
2005
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005
2001
A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller.
IEEE J. Solid State Circuits, 2001
1999
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999
1998
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998