Pascal Urard
According to our database1,
Pascal Urard
authored at least 41 papers
between 2003 and 2024.
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Bibliography
2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
GemIMC: A Configurable HW Architecture for Technology Agnostic IMC Based NN Inference.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Advanced Analog Design Optimization: Comparison Between Reinforcement Learning and Heuristic Algorithms.
Proceedings of the 20th International Conference on Synthesis, 2024
2023
Proceedings of the 19th International Conference on Synthesis, 2023
Performance Modeling and Estimation of a Configurable Output Stationary Neural Network Accelerator.
Proceedings of the 35th IEEE International Symposium on Computer Architecture and High Performance Computing, 2023
Proceedings of the International Joint Conference on Neural Networks, 2023
Static nonlinear errors compensation for RF front-end circuit on high speed RF sampling (Ti)ADCs.
Proceedings of the 2023 IEEE International Conference on Design, 2023
2022
40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
2020
Software Controlled Low Cost Thermoelectric Energy Harvester for Ultra-Low Power Wireless Sensor Nodes.
IEEE Access, 2020
2015
IEEE Internet Things J., 2015
A self-powered IPv6 bidirectional wireless sensor & actuator network for indoor conditions.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
2012
Internet-of-energy: combining embedded computing and communication for the smart grid.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE Trans. Commun., 2010
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Static Address Generation Easing: a design methodology for parallel interleaver architectures.
Proceedings of the IEEE International Conference on Acoustics, 2010
A new approach for minimizing buffer capacities with throughput constraint for embedded system design.
Proceedings of the 8th ACS/IEEE International Conference on Computer Systems and Applications, 2010
2009
IEEE Des. Test Comput., 2009
A 1GHz digital channel multiplexer for satellite OutDoor Unit based on a 65nm CMOS transceiver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable Devices.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Symposium on Information Theory, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
2007
CoRR, 2007
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of IEEE International Conference on Communications, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 15th European Signal Processing Conference, 2007
2006
Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems.
EURASIP J. Adv. Signal Process., 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3).
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 42nd Design Automation Conference, 2005
IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2003
An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003