Pascal Andreas Meinerzhagen
Orcid: 0000-0002-5444-5772
According to our database1,
Pascal Andreas Meinerzhagen
authored at least 36 papers
between 2011 and 2025.
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Bibliography
2025
Recap of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'24).
IEEE Des. Test, February, 2025
2024
IEEE Des. Test, February, 2024
2023
A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2020
An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop.
IEEE J. Solid State Circuits, 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization.
Proceedings of the IEEE International Test Conference, 2020
2019
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits, 2019
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement.
ACM Trans. Design Autom. Electr. Syst., 2016
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS.
Proceedings of the ESSCIRC 2014, 2014
2013
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the ESSCIRC 2013, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
Benchmarking of Standard-Cell Based Memories in the Sub- V<sub>T</sub> Domain in 65-nm CMOS Technology.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011