Parthasarathy P. Tirumalai

According to our database, Parthasarathy P. Tirumalai authored at least 7 papers between 1990 and 1992.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1992

Register Allocation for Software Pipelined Loops.

B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker

Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation (PLDI), 1992

Code generation schema for modulo scheduled loops.

B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing.

Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

1991

Parallelization of WHILE loops on pipelined architectures.

Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker

J. Supercomput., 1991

Minimization Algorithms for Multiple-Valued Programmable Logic Arrays.

Parthasarathy P. Tirumalai, Jon T. Butler

IEEE Trans. Computers, 1991

Parallel Algorithms for Minimizing Multiple-Valued Programmable Logic Arrays.

Parthasarathy P. Tirumalai, Varadarajan G. Vadakkencherry

Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991

1990

Parallelization of loops with exits on pipelined architectures.

Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker

Proceedings of the Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, 1990