Partha Sarathi Paul

Orcid: 0000-0002-8868-5854

Affiliations:
  • University of Mississippi, Department of Electrical and Computer Engineering, University, MS, USA


According to our database1, Partha Sarathi Paul authored at least 12 papers between 2021 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Robust Chaos With Novel 4-Transistor Maps.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Compact Analog Chaotic Map Designs Using SOI Four-Gate Transistors.
IEEE Access, 2023

Split-Slope Chaotic Map Providing High Entropy Across Wide Range.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022
A 2D Chaotic Oscillator for Analog IC.
IEEE Open J. Circuits Syst., 2022

Cascading CMOS-Based Chaotic Maps for Improved Performance and Its Application in Efficient RNG Design.
IEEE Access, 2022

Design, Analysis, and Application of Flipped Product Chaotic System.
IEEE Access, 2022

2021
Design of a Dynamic Parameter-Controlled Chaotic-PRNG in a 65nm CMOS process.
CoRR, 2021

Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map.
CoRR, 2021

Design of a Weighted Average Chaotic System for Robust Chaotic Operation.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Design and Application of a Novel 4-Transistor Chaotic Map with Robust Performance.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

Self-Parameterized Chaotic Map: A Hardware-efficient Scheme Providing Wide Chaotic Range.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

Design of a Low-Overhead Random Number Generator Using CMOS-based Cascaded Chaotic Maps.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021


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