Partha Pratim Pande

Nitthilan Kannappan Jayakodi

ACM Trans. Design Autom. Electr. Syst., 2019

MOOS: A Multi-Objective Design Space Exploration and Optimization Framework for NoC Enabled Manycore Systems.

[BibT_eX]

[DOI]

Aryan Deshwal

Biresh Kumar Joardar

ACM Trans. Embed. Comput. Syst., 2019

Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture.

[BibT_eX]

[DOI]

Dongjin Lee

Integr., 2019

Inter-Tier Process Variation-Aware Monolithic 3D NoC Architectures.

[BibT_eX]

[DOI]

CoRR, 2019

NoC-enabled software/hardware co-design framework for accelerating <i>k-mer</i> counting.

[BibT_eX]

[DOI]

Sriram Krishnamoorthy

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

A Brief Survey of Algorithms, Architectures, and Challenges toward Extreme-scale Graph Analytics.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Design and Optimization of Heterogeneous Manycore Systems Enabled by Emerging Interconnect Technologies: Promises and Challenges.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Scalable Network-on-Chip Architectures for Brain-Machine Interface Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

High-Performance and Small-Form Factor Near-Field Inductive Coupling for 3-D NoC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

A 16-Gb/s Low-Power Inductorless Wideband Gain-Boosted Baseband Amplifier With Skewed Differential Topology for Wireless Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated CMOS Ring PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip.

[BibT_eX]

[DOI]

Nitthilan Kannappan Jayakodi

ACM Trans. Design Autom. Electr. Syst., 2018

Trading-Off Accuracy and Energy of Deep Inference on Embedded Systems: A Co-Design Approach.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

Design Space Exploration of 3D Network-on-Chip: A Sensitivity-based Optimization Approach.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2018

A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Machine Learning and Manycore Systems Design: A Serendipitous Symbiosis.

[BibT_eX]

[DOI]

Computer, 2018

Special session on bringing cores closer together: The wireless revolution in on-chip communication.

[BibT_eX]

[DOI]

Terrence S. T. Mak

Hiroki Matsutani

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Abetting Planned Obsolescence by Aging 3D Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Machine learning for design space exploration and optimization of manycore systems.

[BibT_eX]

[DOI]

Ryan Gary Kim

Proceedings of the International Conference on Computer-Aided Design, 2018

Hybrid on-chip communication architectures for heterogeneous manycore systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

High performance collective communication-aware 3D Network-on-Chip architectures.

[BibT_eX]

[DOI]

Biresh Kumar Joardar

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Imitation Learning for Dynamic VFI Control in Large-Scale Manycore Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Multicast-Aware High-Performance Wireless Network-on-Chip Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Enabling High-Performance SMART NoC Architectures Using On-Chip Wireless Links.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

VFI-Based Power Management to Enhance the Lifetime of High-Performance 3D NoCs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2017

Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

A Reconfigurable Wireless NoC for Large Scale Microbiome Community Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

3D NoC-Enabled Heterogeneous Manycore Architectures for Accelerating CNN Training: Performance and Thermal Trade-offs.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Energy and Area Efficient Near Field Inductive Coupling: A Case Study on 3D NoC.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Performance-thermal trade-offs for a VFI-enabled 3D NoC architecture.

[BibT_eX]

[DOI]

Dongjin Lee

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Monolithic 3D-Enabled High Performance and Energy Efficient Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Energy-efficient and robust 3D NoCs with contactless vertical links (Invited paper).

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Performance evaluation and design trade-offs for wireless-enabled SMART NoC.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noise.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Accelerating Graph Community Detection with Approximate Updates via an Energy-Efficient NoC.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Data analytics enables energy-efficiency and robustness: from mobile to manycores, datacenters, and networks (special session paper).

[BibT_eX]

[DOI]

Sudeep Pasricha

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

2016

Network-on-Chip-Enabled Multicore Platforms for Parallel Model Predictive Control.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

High-Performance and Energy-Efficient Network-on-Chip Architectures for Graph Analytics.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2016

On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Introduction to special issue on International Green Computing Conference (IGCC) 2014.

[BibT_eX]

[DOI]

Sustain. Comput. Informatics Syst., 2016

A dynamic, compiler guided DVFS mechanism to achieve energy-efficiency in multi-core processors.

[BibT_eX]

[DOI]

Teng Lu

Behrooz A. Shirazi

Sustain. Comput. Informatics Syst., 2016

Fast Uncovering of Graph Communities on a Chip: Toward Scalable Community Detection on Multicore and Manycore Platforms.

[BibT_eX]

[DOI]

Daniel G. Chavarría-Miranda

Mahantesh Halappanavar

Hao Lu

Found. Trends Electron. Des. Autom., 2016

Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3D Small-world Network-on-Chip.

[BibT_eX]

[DOI]

CoRR, 2016

The Future of NoCs: New Technologies and Architectures.

[BibT_eX]

[DOI]

Sudeep Pasricha

Hiroki Matsutani

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Tutorial 3A: Bringing cores closer together: The wireless revolution in on-chip communication.

[BibT_eX]

[DOI]

Jürgen Becker

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs.

[BibT_eX]

[DOI]

Sheng-En David Lin

Dae Hyun Kim

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Reliability and performance trade-offs for 3D NoC-enabled multicore chips.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Making the internet-of-things a reality: from smart models, sensing and actuation to energy-efficient architectures.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous manycore platforms.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Compilers, 2016

Power and thermal management in massive multicore chips: theoretical foundation meets architectural innovation and resource allocation.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Compilers, 2016

2015

Introduction to IEEE Transactions on Multiscale Computing Systems (TMSCS).

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2015

An 18.7-Gb/s 60-GHz OOK Demodulator in 65-nm CMOS for Wireless Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

DVFS Pruning for Wireless NoC Architectures.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

Improving EDP in wireless NoC-enabled multicore chips via DVFS pruning.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Enhancing performance of wireless NoCs with distributed MAC protocols.

[BibT_eX]

[DOI]

Ryan Gary Kim

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

The (Low) Power of Less Wiring: Enabling Energy Efficiency in Many-Core Platforms Through Wireless NoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

On-chip network-enabled many-core architectures for computational biology applications.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

NoC-enabled multicore architectures for stochastic analysis of biomolecular reactions.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Energy efficient MapReduce with VFI-enabled multicore platforms.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

High performance and energy efficient wireless NoC-enabled multicore architectures for graph analytics.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Compilers, 2015

2014

Design Space Exploration for Wireless NoCs Incorporating Irregular Network Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Dual-Level DVFS-Enabled Millimeter-Wave Wireless NoC Architectures.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

Performance Evaluation of Congestion-Aware Routing with DVFS on a Millimeter-Wave Small-World Wireless NoC.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip.

[BibT_eX]

[DOI]

Haera Chung

Christof Teuscher

ACM J. Emerg. Technol. Comput. Syst., 2014

Architecture and Design of Multichannel Millimeter-Wave Wireless NoC.

[BibT_eX]

[DOI]

IEEE Des. Test, 2014

Wireless NoC Platforms With Dynamic Task Allocation for Maximum Likelihood Phylogeny Reconstruction.

[BibT_eX]

[DOI]

IEEE Des. Test, 2014

Hardware Accelerators in Computational Biology: Application, Potential, and Challenges.

[BibT_eX]

[DOI]

IEEE Des. Test, 2014

T1B: Wireless NoC as interconnection backbone for multicore chips: Promises and challenges.

[BibT_eX]

[DOI]

Alireza Nojeh

André Ivanov

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

T2B: Carbon nanotubes and opportunities for wireless on-chip interconnect.

[BibT_eX]

[DOI]

Alireza Nojeh

André Ivanov

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Introduction to the special session on "Interconnect enhances architecture: Evolution of wireless NoC from planar to 3D".

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

An energy-efficient millimeter-wave wireless NoC with congestion-aware routing and DVFS.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Thermal hotspot reduction in mm-Wave wireless NoC architectures.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Performance evaluation of wireless NoCs in presence of irregular network routing strategies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy-efficient VFI-partitioned multicore design using wireless NoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Compilers, 2014

2013

Sustainable and Reliable On-Chip Wireless Communication Infrastructure for Massive Multi-core Systems.

[BibT_eX]

[DOI]

Proceedings of the Evolutionary Based Solutions for Green Computing, 2013

Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

High-throughput, energy-efficient network-on-chip-based hardware accelerators.

[BibT_eX]

[DOI]

Sustain. Comput. Informatics Syst., 2013

Complex network-enabled robust wireless network-on-chip architectures.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2013

Sustainable DVFS-Enabled Multi-Core Architectures with On-Chip Wireless Links.

[BibT_eX]

[DOI]

Adv. Comput., 2013

Millimeter (mm)-wave wireless NoC as interconnection backbone for multicore chips: promises and challenges.

[BibT_eX]

[DOI]

Proceedings of the Network on Chip Architectures, 2013

Sustainable dual-level DVFS-enabled NoC with on-chip wireless links.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Network-on-Chip with Long-Range Wireless Links for High-Throughput Scientific Computation.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Evaluating effects of thermal management in wireless NoC-enabled multicore architectures.

[BibT_eX]

[DOI]

Proceedings of the International Green Computing Conference, 2013

Energy-efficient multicore chip design through cross-layer approach.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Design space exploration for reliable mm-wave wireless NoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012

Energy-Efficient Network-on-Chip Architectures for Multi-Core Systems.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

On-Chip Network-Enabled Multicore Platforms Targeting Maximum Likelihood Phylogeny Reconstruction.

[BibT_eX]

[DOI]

Michael Edward Borgens

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

NoC-Based Hardware Accelerator for Breakpoint Phylogeny.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

Introduction to the special issue on sustainable and green computing systems.

[BibT_eX]

[DOI]

Amlan Ganguly

ACM J. Emerg. Technol. Comput. Syst., 2012

Performance evaluation and design trade-offs for wireless network-on-chip architectures.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2012

Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Test Technology TC Newsletter.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2012

DVFS-enabled sustainable wireless NoC architecture.

[BibT_eX]

[DOI]

Jacob Murray

Behrooz A. Shirazi

Proceedings of the IEEE 25th International SOC Conference, 2012

Design of an efficient NoC architecture using millimeter-wave wireless links.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Sustainable multi-core architecture with on-chip wireless links.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

Three-Dimensional Networks-on-Chip: Performance Evaluation.

[BibT_eX]

[DOI]

Brett Stanley Feero

Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Guest editorial.

[BibT_eX]

[DOI]

Sanjay Ranka

Sustain. Comput. Informatics Syst., 2011

Accelerating Maximum Likelihood Based Phylogenetic Kernels Using Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011

Complex network inspired fault-tolerant NoC architectures with wireless links.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2011, 2011

A Unified Error Control Coding Scheme to Enhance the Reliability of a Hybrid Wireless Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Sustainability through massively integrated computing: Are we ready to break the energy efficiency wall for single-chip platforms?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Network-on-Chip Hardware Accelerators for Biological Sequence Alignment.

[BibT_eX]

[DOI]

Souradip Sarkar

Gaurav Ramesh Kulkarni

IEEE Trans. Computers, 2010

Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies.

[BibT_eX]

[DOI]

Sriram R. Vangal

IEEE Des. Test Comput., 2010

Comparative performance evaluation of wireless and optical NoC architectures.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Hardware accelerators for biocomputing: A survey.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Unconventional fabrics, architectures, and models for future multi-core systems.

[BibT_eX]

[DOI]

Radu Marculescu

Christof Teuscher

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009

Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects.

[BibT_eX]

[DOI]

Amlan Ganguly

Benjamin Belzer

IEEE Trans. Very Large Scale Integr. Syst., 2009

Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation.

[BibT_eX]

[DOI]

Brett Feero

IEEE Trans. Computers, 2009

Networks-on-chip in emerging interconnect paradigms: Advantages and challenges.

[BibT_eX]

[DOI]

Luca P. Carloni

Yuan Xie

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Hybrid wireless Network on Chip: a new paradigm in multi-core design.

[BibT_eX]

[DOI]

Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

Performance evaluation of wireless networks on chip architectures.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Energy reduction through crosstalk avoidance coding in networks on chip.

[BibT_eX]

[DOI]

J. Syst. Archit., 2008

Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

Novel interconnect infrastructures for massive multicore chips - an overview.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Testing Network-on-Chip Communication Fabrics.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Multiple clock domain synchronization for network on chip architectures.

[BibT_eX]

[DOI]

Jabulani Nyathi

Souradip Sarkar

Proceedings of the 2007 IEEE International SOC Conference, 2007

Towards Open Network-on-Chip Benchmarks.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Performance Evaluation for Three-Dimensional Networks-On-Chip.

[BibT_eX]

[DOI]

Brett Feero

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Essential Fault-Tolerance Metrics for NoC Infrastructures.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics.

[BibT_eX]

[DOI]

Haibo Zhu

Cristian Grecu

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

System-on-Chip: Reuse and Integration.

[BibT_eX]

[DOI]

Proc. IEEE, 2006

BIST for Network-on-Chip Interconnect Infrastructures.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Crosstalk-aware Energy Reduction in NoC Communication Fabrics.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

On-line Fault Detection and Location for NoC Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

NoC Interconnect Yield Improvement Using Crosspoint Redundancy.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Timing analysis of network on chip architectures for MP-SoC platforms.

[BibT_eX]

[DOI]

Microelectron. J., 2005

Design, Synthesis, and Test of Networks on Chips.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2005

Effect of traffic localization on energy dissipation in NoC-based interconnect.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Methodologies and Algorithms for Testing Switch-Based NoC Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004

A Scalable Communication-Centric SoC Interconnect Architecture.

[BibT_eX]

[DOI]

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003

High-Throughput Switch-Based Interconnect for Future SoCs.

[BibT_eX]

[DOI]