Partha Mitra

Orcid: 0000-0002-1331-3538

According to our database1, Partha Mitra authored at least 8 papers between 1998 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
A CAD approach for power supply noise aware floorplan in SoC.
Int. J. High Perform. Syst. Archit., 2021

Decoupling Capacitor Estimation and Allocation using Optimization Techniques for Power Supply Noise Reduction in System-on-Chip.
J. Electron. Test., 2021

2020
Soft Computing Techniques Based CAD Approach for Power Supply Noise Reduction in System-on-Chip.
J. Electron. Test., 2020

2018
Overfitting or perfect fitting? Risk bounds for classification and regression rules that interpolate.
Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018

Implementation of Universal Modulator Using CORDIC Architecture in FPGA.
Proceedings of the Computational Intelligence, Communications, and Business Analytics, 2018

2016
Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015
Pre-Layout Decoupling Capacitance Estimation and Allocation for Noise-Aware Crypto-System on Chip Applications.
J. Low Power Electron., 2015

1998
A detection framework for locating phonetic events.
Proceedings of the 5th International Conference on Spoken Language Processing, Incorporating The 7th Australian International Speech Science and Technology Conference, Sydney Convention Centre, Sydney, Australia, 30th November, 1998


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