Parth Malani

Orcid: 0009-0001-0589-5048

According to our database1, Parth Malani authored at least 15 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Revisiting Reliability in Large-Scale Machine Learning Research Clusters.
CoRR, 2024

Dynamic Idle Resource Leasing To Safely Oversubscribe Capacity At Meta.
Proceedings of the 2024 ACM Symposium on Cloud Computing, 2024

Expanding Datacenter Capacity with DVFS Boosting: A safe and scalable deployment experience.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Tutorial: MARS: A Framework for Runtime Monitoring, Modeling, and Management of Realtime Systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

2022
Interference and Need Aware Workload Colocation in Hyperscale Datacenters.
CoRR, 2022

2021
Transitive Power Modeling for Improving Resource Efficiency in a Hyperscale Datacenter.
Proceedings of the Companion of The Web Conference 2021, 2021

2018
Deep Learning Inference in Facebook Data Centers: Characterization, Performance Optimizations and Hardware Implications.
CoRR, 2018

2014
Accelerating pattern matching in neuromorphic text recognition system using Intel Xeon Phi coprocessor.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

2012
Low Power Task Scheduling and Mapping for Applications with Conditional Branches on Heterogeneous Multi-Processor System.
J. Low Power Electron., 2012

2010
Distributed task migration for thermal management in many-core systems.
Proceedings of the 47th Design Automation Conference, 2010

2008
Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-time Applications with Non-deterministic Workload.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Power optimization for conditional task graphs in DVS enabled multiprocessor systems.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Profile-Based Low Power Scheduling for Conditional Task Graph: A Communication Aware Approach.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Resource-aware High Performance Scheduling for Embedded MPSoCs With the Application of MPEG Decoding.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

2006
Workload prediction and dynamic voltage scaling for MPEG decoding.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006


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