Paritosh Bhoraskar

According to our database, Paritosh Bhoraskar authored at least 7 papers between 2010 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration.

Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Bardsley, Christopher Dillon, Matthew McShea, Joel Prabhakar, Scott Puckett

IEEE J. Solid State Circuits, 2020

16.1 A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration.

Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Bardsley, Christopher Dillon, Mohit Kumar, Matthew McShea, Ryan Bunch, Joel Prabhakar, Scott Puckett

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2016

A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither.

Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Puckett, Andy Morgan, Ning Zhu, Qicheng Yu, Christopher Dillon, Bryce Gray, Jonathan Lanford, Matthew McShea, Ushma Mehta, Scott Bardsley, Peter R. Derounian, Ryan Bunch, Ralph Moore, Gerry Taylor

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2014

A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration.

Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Christopher Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Russell Stop

IEEE J. Solid State Circuits, 2014

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration.

Ahmed M. Abdelatty Ali, Hüseyin Dinc, Paritosh Bhoraskar, Christopher Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, David Jarman, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Ho-Young Lee

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2010

A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration.

Ahmed M. A. Ali, Andrew S. Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Paritosh Bhoraskar, Hüseyin Dinc, Mike Hensley, Russell Stop, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed

IEEE J. Solid State Circuits, 2010

A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration.

Ahmed M. A. Ali, Andy Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Mike Hensley, Russell Stop, Paritosh Bhoraskar, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed

Proceedings of the IEEE International Solid-State Circuits Conference, 2010