Parimal Pal Chaudhuri

Affiliations:
  • CARLBio Pvt. Ltd., Kolkata, India
  • Techno India College of Technology, Cellular Automata Research Lab (CARL), Kolkata, India
  • Bengal Engineering College, Howrah, India
  • Intel Research Labs, Portland, OR, USA
  • Indian Institute of Technology Kharagpur, India (PhD 1979)


According to our database1, Parimal Pal Chaudhuri authored at least 124 papers between 1985 and 2023.

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Bibliography

2023
Cellular Automata-Based Sentiment Analysis.
Proceedings of Second Asian Symposium on Cellular Automata Technology, 2023

2022
Analysis of coronavirus envelope protein with cellular automata model.
Int. J. Parallel Emergent Distributed Syst., 2022

Cellular Automata Model for Non-Structural Proteins Comparing Transmissibility and Pathogenesis of SARS Covid (CoV-2, CoV) and MERS Covid.
CoRR, 2022

Analysis of Coronavirus Envelope Protein with Cellular Automata (CA) Model.
CoRR, 2022

2018
Cellular Automata Model for Proteomics and Its Application in Cancer Immunotherapy.
Proceedings of the Cellular Automata, 2018

A New Kind of Computational Biology - Cellular Automata Based Models for Genomics and Proteomics
Springer, ISBN: 978-981-13-1638-8, 2018

2014
Cellular Automata (CA) Model for Primality Test.
Proceedings of the Cellular Automata, 2014

Cellular Automata Model for Protein Structure Synthesis (PSS).
Proceedings of the Cellular Automata, 2014

2012
Rule Vector Graph (RVG) To Design Linear Time Algorithm for Identifying the Invertibility of Periodic-Boundary Three Neighborhood Cellular Automata.
J. Cell. Autom., 2012

Theory and Application of Restricted Five Neighborhood Cellular Automata (R5NCA) for Protein Structure Prediction.
Proceedings of the Cellular Automata, 2012

2011
On Invertible Three Neighborhood Null-Boundary Uniform Cellular Automata.
Complex Syst., 2011

2010
Linear Time Algorithm for Identifying the Invertibility of Null-Boundary Three Neighborhood Cellular Automata.
Complex Syst., 2010

Programmable Cellular Automata (PCA) Based Advanced Encryption Standard (AES) Hardware Architecture.
Proceedings of the Cellular Automata, 2010

Theory and Application of Equal Length Cycle Cellular Automata (ELCCA) for Enzyme Classification.
Proceedings of the Cellular Automata, 2010

2008
Fault Diagnosis of Electronic Circuits Using Cellular Automata Based Pattern Classifier.
Proceedings of the Soft Computing Applications in Industry, 2008

An Analytical Framework for Characterizing Restricted Two Dimensional Cellular Automata Evolution.
J. Cell. Autom., 2008

Non-uniform cellular automata based associative memory: Evolutionary design and basins of attraction.
Inf. Sci., 2008

Exploring Cycle Structures of Additive Cellular Automata.
Fundam. Informaticae, 2008

2007
RBFFCA: A Hybrid Pattern Classifier Using Radial Basis Function and Fuzzy Cellular Automata.
Fundam. Informaticae, 2007

Design of Response-Pattern Classi er for Fault Diagnosis of Electronic Circuits.
Proceedings of the 3rd Indian International Conference on Artificial Intelligence, 2007

Probabilistic Cellular Automata Model for Identification of CpG island in DNA String.
Proceedings of the 3rd Indian International Conference on Artificial Intelligence, 2007

2006
An Analytical Formulation for Cellular Automata (CA) Based Solution of Density Classification Task (DCT).
Proceedings of the Cellular Automata, 2006

2005
Fault diagnosis of VLSI circuits with cellular automata based pattern classifier.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Fuzzy Cellular Automata for Modeling Pattern Classifier.
IEICE Trans. Inf. Syst., 2005

Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time.
J. Electron. Test., 2005

2004
Design and characterization of cellular automata based associative memory for pattern recognition.
IEEE Trans. Syst. Man Cybern. Part B, 2004

Synthesis of programmable multi-input current-mode linear analog circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Generation of test patterns without prohibited pattern set.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Cellular Automata Based Pattern Classifying Machine for Distributed Data Mining.
Proceedings of the Neural Information Processing, 11th International Conference, 2004

FMACA: A Fuzzy Cellular Automata Based Pattern Classifier.
Proceedings of the Database Systems for Advances Applications, 2004

Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

An efficient design of non-linear <i>CA</i> based PRPG for VLSI circuit testing.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Cellular Automata Based Encompression Technology for Voice Data.
Proceedings of the Cellular Automata, 2004

Cellular Automata Evolution for Pattern Classification.
Proceedings of the Cellular Automata, 2004

Cellular Automata Evolution for Distributed Data Mining.
Proceedings of the Cellular Automata, 2004

Characterization of Reachable/Nonreachable Cellular Automata States.
Proceedings of the Cellular Automata, 2004

2003
Error correcting capability of cellular automata based associative memory.
IEEE Trans. Syst. Man Cybern. Part A, 2003

Theory and Application of Cellular Automata For Pattern Classification.
Fundam. Informaticae, 2003

A Pipeline Architecture for Encompression (Encryption + Compression) Technology.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Cryptosystem Designed for Embedded System Security.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Synthesis Of Programmable Current Mode Linear Analog Circuit.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Design Of A Universal BIST (UBIST) Structure.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Application of Fuzzy Cellular Automata (FCA) For Modeling Tree-Structured Pattern Classifier.
Proceedings of the 1st Indian International Conference on Artificial Intelligence, 2003

Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Design of hierarchical cellular automata for on-chip test pattern generator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Efficient synthesis of OTA network for linear analog functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Theory of Extended Linear Machines.
IEEE Trans. Computers, 2002

Generalized Multiple Attractor Cellular Automata (GMACA) Model for Associative Memory.
Int. J. Pattern Recognit. Artif. Intell., 2002

Test Solution for OTA Based Analog Circuits.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS).
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Cellular Automata Based Cryptosystem (CAC).
Proceedings of the Information and Communications Security, 4th International Conference, 2002

An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS).
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Characterization of Non-linear Cellular Automata Model for Pattern Recognition.
Proceedings of the Advances in Soft Computing, 2002

Cellular Automata Based Authentication (CAA).
Proceedings of the Cellular Automata, 2002

Cellular Automata Machine for Pattern Recognition.
Proceedings of the Cellular Automata, 2002

Evolving Cellular Automata as Pattern Classifier.
Proceedings of the Cellular Automata, 2002

2001
Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator.
IEEE Trans. Computers, 2001

Hierarchical Cellular Automata As An On-Chip Test Pattern Generator.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Evolving Cellular Automata Based Associative Memory for Pattern Recognition.
Proceedings of the High Performance Computing - HiPC 2001, 8th International Conference, 2001

Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Cellular automata as a built in self test structure.
Proceedings of ASP-DAC 2001, 2001

2000
Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Design of OTA Based Field Programmable Analog Array.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Scalable Pipelined Micro-Architecture for Wavelet Transform.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Theory and Applications of Cellular Automata for VLSI Design and Testing.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Fsimac: a fault simulator for asynchronous sequential circuits.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A VLSI Architecture for Cellular Automata Based Reed-Solomon Decoder.
Proceedings of the 1999 International Symposium on Parallel Architectures, 1999

Cellular Automata Based Transform Coding for Image Compression.
Proceedings of the High Performance Computing, 1999

1998
Cellular-Automata-Array-Based Diagnosis of Board Level Faults.
IEEE Trans. Computers, 1998

Efficient Signatures with Linear Space Complexity for Detecting Boolean Function Equivalence.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine Synthesis.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Reply to Comments on "Theory and Application of Cellular Automata in Cryptography".
IEEE Trans. Computers, 1997

Parallel Decoder for Cellular Automata Based Byte Error Correcting Code.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Parallel Architecture for Video Compression.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996
CAA Decoder for Cellular Automata Based Byte Error Correcting Code.
IEEE Trans. Computers, 1996

Analysis of Periodic and Intermediate Boundary 90/150 Cellular Automata.
IEEE Trans. Computers, 1996

Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach.
IEEE Trans. Computers, 1996

Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines.
IEEE Trans. Computers, 1996

Programmable cellular automata based testbed for fault diagnosis in VLSI circuits.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Architecture of a VLSI Chip for Modeling Amino Acid Sequence in Proteins.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Cellular automata based architecture of a database query processor.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A VLSI architecture for cellular automata based parallel data compression.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

An efficient encoding algorithm for image compression hardware based on cellular automata.
Proceedings of the 3rd International Conference on High Performance Computing, 1996

1995
CA-Based Byte Error-Correcting Code.
IEEE Trans. Computers, 1995

A Low-Cost High-Capacity Associative Memory Design Using Cellular Automata.
IEEE Trans. Computers, 1995

Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Board level fault diagnosis using cellular automata array.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Theory and applications of cellular automata for synthesis of easily testable combinational logic.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Panel: New Research Problems in the Emerging Test Technology.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994
Theory and Applications of Cellular Automata in Cryptography.
IEEE Trans. Computers, 1994

Design of CAECC-Cellular Automata Based Error Correcting Code.
IEEE Trans. Computers, 1994

A class of two-dimensional cellular automata and their applications in random pattern testing.
J. Electron. Test., 1994

A CAD Tool for Design of On-Chip Store & Generate Scheme.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Architecture for VLSI Design of CA Based Byte Error Correcting Code Decoders.
Proceedings of the Seventh International Conference on VLSI Design, 1994

1993
Vector Space Theoretic Analysis of Additive Cellular Automata and Its Application for Pseudoexhaustive Test Pattern Generation.
IEEE Trans. Computers, 1993

On explicit expressions in additive cellular automata theory.
Inf. Sci., 1993

Characterization of two-dimensional cellular automata using matrix algebra.
Inf. Sci., 1993

Estimating the Complexity of Synthesized Designs from FSM Specifications.
IEEE Des. Test Comput., 1993

Delay Fault Test Generation with Cellular Automata.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A Scheme for Synthesizing Testable VLSI Designs with Minimum Area Overhead.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A Novel Scheme for Synthesis of Easily Testable Finite State Machines Using Cellular Automata.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Synthesis of Self-Checking Sequential Machines Using Cellular Automata.
Proceedings of the Sixth International Conference on VLSI Design, 1993

1992
On characterization of cellular automata with matrix algebra.
Inf. Sci., 1992

On characterization of state transition graph of additive cellular automata based on depth.
Inf. Sci., 1992

An Efficient State Assignment Technique using Least Commitment and Constraint Propagation Techniques.
Proceedings of the Fifth International Conference on VLSI Design, 1992

Combined Synthesis of Easily Testable Datapath and Control Designs.
Proceedings of the Fifth International Conference on VLSI Design, 1992

Synthesis of Self-Testable Sequential Logic Using Programmable Cellular Automata.
Proceedings of the Fifth International Conference on VLSI Design, 1992

A Novel Scheme for Designing Error Correcting Codes Using Cellular Automata.
Proceedings of the Fifth International Conference on VLSI Design, 1992

1991
A Flexible Scheme for State Assignment Based on Characteristics of the FSM.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
Signature analysers based on additive cellular automata.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

1989
Design of Testable VLSI Circuits with Minumum Area Overhead.
IEEE Trans. Computers, 1989

Expert system to configure global design for testability structure in a VLSI circuit.
Microprocess. Microsystems, 1989

An efficient on-chip deterministic test pattern generation scheme.
Microprocessing and Microprogramming, 1989

KIDLAN: A hardware description language.
Microprocessing and Microprogramming, 1989

Selecting test methodologies for PLAs and random logic modules in VLSI circuits - an expert systems approach.
Integr., 1989

DFT Expert: designing testable VLSI circuits.
IEEE Des. Test, 1989

1988
DFTEXPERT: An Expert System for Design of Testable VLSI Circuits.
Proceedings of the First International Conference on Industrial & Engineering Applications of Artificial Intelligence & Expert Systems, IEA/AIE 1988, June 1-3, 1988, Tullahoma, TN, USA. ACM, 1988, 1988

1986
A Divide and Conquer Testing Strategy for Detection of Multiple Faults by SFDTS.
Proceedings of the Proceedings International Test Conference 1986, 1986

1985
Design of a 'T' Fault Repairable Multiprocessor System.
Proceedings of the 5th International Conference on Distributed Computing Systems, 1985


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