Paraskevas Kalivas

According to our database1, Paraskevas Kalivas authored at least 9 papers between 2000 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2005
A New Low Latency Parallel FIR Filter Scheme.
J. VLSI Signal Process., 2005

Pipelined array-based FIR filter folding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Novel systolic schemes for serial-parallel multiplication.
Proceedings of the 13th European Signal Processing Conference, 2005

100% operational efficient bit-serial programmable FIR digital filters.
Proceedings of the 13th European Signal Processing Conference, 2005

Long Number Bit-Serial Squarers.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004
Low-latency and high-efficiency bit serial-serial multipliers.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

Pipeline array implementation of FIR filters.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

2000
Constant Number Serial Pipeline Multipliers.
J. VLSI Signal Process., 2000

A systolic serial squarer of continuous operation.
Proceedings of the 10th European Signal Processing Conference, 2000


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