Paras Garg

According to our database¹, Paras Garg authored at least 2 papers in 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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2024

A Novel 2.7 pJ/bit, Low Supply, Power Efficient, Wide-Range 2.5-6 Gb/s Transmitter for 4-Channel High-Speed Serial Transmit Port (HSSTP) in 28nm FD-SOI Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Loop Filter Design Considerations for Noise-Shaping in SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Paras Garg

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