Parag Upadhyaya

According to our database, Parag Upadhyaya authored at least 33 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2024

A 64 Gb/s NRZ O-Band Ring Modulator with 3.2 THz FSR for DWDM Applications.

Chuan Xie, Mayank Raj, Anish Joshi, Zakriya Mohammed, Gareeyasee Saha, Zhaowen Wang, Parag Upadhyaya, Yohan Frans

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2024

2023

A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies.

Mayank Raj, Chuan Xie, Ade Bekele, Adam Chou, Wenfeng Zhang, Ying Cao, Jae Wook Kim, Nakul Narang, Hongyuan Zhao, Yipeng Wang, Kee Hian Tan, Winson Lin, Jay Im, David Mahashin, Santiago Asuncion, Parag Upadhyaya, Yohan Frans

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET.

Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans

IEEE J. Solid State Circuits, 2022

2021

A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET.

Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2019

A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.

Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang

IEEE J. Solid State Circuits, 2019

2018

A 112-GB/S PAM4 Transmitter in 16NM FinFET.

Kee Hian Tan, Ping-Chuan Chiang, Yipeng Wang, Haibing Zhao, Arianne Roldan, Hongyuan Zhao, Nakul Narang, Siok-Wei Lim, Declan Carey, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.

Jay Im, Stanley Chen, Dave Freitas, Adam Chou, Lei Zhou, Ian Zhuang, Tim Cronin, David Mahashin, Winson Lin, Kok Lim Chan, Hongyuan Zhao, Kee Hian Tan, Ade Bekele, Didem Turker, Parag Upadhyaya, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.

James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET.

Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs.

Didem Turker, Ade Bekele, Parag Upadhyaya, Bob Verbruggen, Ying Cao, Shaojun Ma, Christophe Erdmann, Brendan Farley, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET.

Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang

IEEE J. Solid State Circuits, 2017

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET.

Yohan Frans, Jaewook Shin, Lei Zhou, Parag Upadhyaya, Jay Im, Vassili Kireev, Mohamed Elzeftawi, Hiva Hedayati, Toan Pham, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang

IEEE J. Solid State Circuits, 2017

A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET.

Marc Erett, James Hudner, Declan Carey, Ronan Casey, Kevin Geary, Kay Hearne, Pedro Neto, Thomas Mallard, Vikas Sooden, Mark Smyth, Yohan Frans, Jay Im, Parag Upadhyaya, Wenfeng Zhang, Winson Lin, Bruce Xu, Ken Chang

IEEE J. Solid State Circuits, 2017

A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS.

Kok Lim Chan, Kee Hian Tan, Yohan Frans, Jay Im, Parag Upadhyaya, Siok-Wei Lim, Arianne Roldan, Nakul Narang, Chin Yang Koay, Hongyuan Zhao, Ping-Chuan Chiang, Ken Chang

IEEE J. Solid State Circuits, 2017

6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET.

Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET.

Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang

IEEE J. Solid State Circuits, 2016

A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.

Parag Upadhyaya, Ade Bekele, Didem Turkur Melek, Haibing Zhao, Jay Im, Junho Cho, Kee Hian Tan, Scott McLeod, Stanley Chen, Wenfeng Zhang, Yohan Frans, Ken Chang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 7-to-18.3GHz compact transformer based VCO in 16nm FinFET.

Mayank Raj, Parag Upadhyaya, Yohan Frans, Ken Chang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET.

Yohan Frans, Mohamed Elzeftawi, Hiva Hedayati, Jay Im, Vassili Kireev, Toan Pham, Jaewook Shin, Parag Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET.

Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET.

Marc Erett, James Hudner, Declan Carey, Ronan Casey, Kevin Geary, Kay Hearne, Pedro Neto, Thomas Mallard, Vikas Sooden, Mark Smyth, Yohan Frans, Jay Im, Parag Upadhyaya, Wenfeng Zhang, Winson Lin, Bruce Xu, Ken Chang

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS.

Kok Lim Chan, Kee Hian Tan, Yohan Frans, Jay Im, Parag Upadhyaya, Siok-Wei Lim, Arianne Roldan, Nakul Narang, Chin Yang Koay, Hongyuan Zhao, Ken Chang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS.

Yohan Frans, Declan Carey, Marc Erett, Hesam Amir Aslanzadeh, Wayne Y. Fang, Didem Turker, Anup P. Jose, Adebabay Bekele, Jay Im, Parag Upadhyaya, Zhaoyin Daniel Wu, Kenny C.-H. Hsieh, Jafar Savoj, Ken Chang

IEEE J. Solid State Circuits, 2015

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS.

Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup P. Jose, Bruce Xu, Zhaoyin Daniel Wu, Didem Turker, Hesam Amir Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS.

Jun-Chau Chien, Parag Upadhyaya, Howard Jung, Stanley Chen, Wayne Fang, Ali M. Niknejad, Jafar Savoj, Ken Chang

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS.

Jafar Savoj, Hesam Amir Aslanzadeh, Declan Carey, Marc Erett, Wayne Fang, Yohan Frans, Kenny C.-H. Hsieh, Jay Im, Anup P. Jose, Didem Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs.

Jafar Savoj, Kenny C.-H. Hsieh, Fu-Tai An, J. Gong, Jay Im, Xuewen Jiang, Anup P. Jose, Vassili Kireev, Siok-Wei Lim, Arianne Roldan, D. Z. Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang

IEEE J. Solid State Circuits, 2013

2012

A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS.

Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Ade Bekele, Stanley Chen, Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Aman Sewani, Didem Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, Elad Alon, Ken Chang

Proceedings of the Symposium on VLSI Circuits, 2012

Spin wave nanofabric update.

J. G. Alzate, Parag Upadhyaya, M. Lewis, J. Nath, Y. T. Lin, Kin Wong, S. Cherepov, P. Khalili Amiri, Kang L. Wang, J. Hockel, A. Bur, Gregory P. Carman, S. Bender, Y. Tserkovnyak, J. Zhu, Y.-J. Chen, I. N. Krivorotov, J. Katine, J. Langer, Prasad Shabadi, Santosh Khasanvis, Sankara Narayanan Rajapandian, Csaba Andras Moritz, Alexander Khitun

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Design of high-speed wireline transceivers for backplane communications in 28nm CMOS.

Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Jay Im, Xuewen Jiang, Jalil Kamali, Kang Wei Lai, Zhaoyin Daniel Wu, Elad Alon, Ken Chang

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2006

A 5.3GHz low-phase-noise LC VCO with harmonic filtering resistor.

Le Wang, Parag Upadhyaya, Pinping Sun, Yang Zhang, Deuk Hyoun Heo, Yi-Jan Emery Chen, DongHo Jeong

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Enhanced gm3 cancellation for linearity improvement in CMOS LNAs.

Mallesh Rajashekharaiah, Parag Upadhyaya, Deuk Hyoun Heo

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A new gain controllable on-chip active balun for 5 GHz direct conversion receiver.

Mallesh Rajashekharaiah, Parag Upadhyaya, Deuk Hyoun Heo, Yi-Jan Emery Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005