Parag K. Lala
According to our database1,
Parag K. Lala
authored at least 65 papers
between 1981 and 2010.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2001, "For contributions to the development of self-checking logic and associated checker design.".
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Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on tamut.edu
On csauthors.net:
Bibliography
2010
VLSI Design, 2010
A Quantum Key Distribution Protocol.
Proceedings of the 2010 International Conference on Security & Management, 2010
2008
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79785-9, 2008
On FPGA Design with Self-checking and Fault Tolerance Capability.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.
J. Electron. Test., 2007
2006
2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
2004
Logic implementation using a reversible gate.
Proceedings of the Second IASTED International Conference on Circuits, 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
A New Reversible Logic Gate and its Applications.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003
A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
2002
On-line Error Detection in a Carry-free Adder.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
1998
1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
1996
Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set.
IEEE Trans. Computers, 1996
J. Electron. Test., 1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
1995
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995
1994
VLSI Design, 1994
Partially Strongly Fault Secure and Partially Strongly Code Disjoint I-out-of-3 Code Checker.
IEEE Trans. Computers, 1994
Self-checking combinational circuit design for single and unidirectional multibit error.
J. Electron. Test., 1994
1993
Input and output encoding techniques for on-line error detection in combinational logic circuits.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993
1992
IEEE J. Solid State Circuits, August, 1992
A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay.
IEEE Trans. Computers, 1992
IEEE Des. Test Comput., 1992
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992
A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992
1991
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991
1990
A scheme for designing fault-tolerant microprogrammed processors using bit-slice chips.
Microprocessing and Microprogramming, 1990
1988
IEEE J. Solid State Circuits, June, 1988
IEEE Trans. Computers, 1988
1986
A Concurrent Testing Strategy for PLAs.
Proceedings of the Proceedings International Test Conference 1986, 1986
On Built-In Testing of VLSI Chips.
Proceedings of the Proceedings International Test Conference 1986, 1986
1985
Softw. Microsystems, 1985
1984
Microprocess. Microsystems, 1984
1981