Paolo Zicari

Orcid: 0000-0002-9119-9865

According to our database1, Paolo Zicari authored at least 24 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
Towards Data- and Compute-Efficient Fake-News Detection: An Approach Combining Active Learning and Pre-Trained Language Models.
SN Comput. Sci., June, 2024

Boosting MATE Security through Small Language Models.
ERCIM News, 2024

Dawn of LLM4Cyber: Current Solutions, Challenges, and New Perspectives in Harnessing LLMs for Cybersecurity.
Proceedings of the Ital-IA Intelligenza Artificiale, 2024

2023
An Explainable Deep Ensemble Framework for Intelligent Ticket Management.
ERCIM News, 2023

Learning Deep Fake-News Detectors from Scarcely-Labelled News Corpora.
Proceedings of the 25th International Conference on Enterprise Information Systems, 2023

2022
Combining deep ensemble learning and explanation for intelligent ticket management.
Expert Syst. Appl., 2022

2021
Discovering accurate deep learning based predictive models for automatic customer support ticket classification.
Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021

2017
Controversy-Aware Hybrid Trust Inference in Online Social Networks.
Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

2016
Controversy in Trust Networks.
Proceedings of the Trust and Trustworthy Computing - 9th International Conference, 2016

2014
A power-efficient real-time architecture for SURF feature extraction.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

2013
Efficient and high performance FPGA-based rectification architecture for stereo vision.
Microprocess. Microsystems, 2013

2012
Low-cost FPGA stereo vision system for real time disparity maps calculation.
Microprocess. Microsystems, 2012

An embedded system for on field testing of human identification using ECG biometric.
Proceedings of the 11th International Conference on Information Science, 2012

2010
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications.
ACM Trans. Reconfigurable Technol. Syst., 2010

2009
Designing High-Speed Adders in Power-Constrained Environments.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Low-power split-path data-driven dynamic logic.
IET Circuits Devices Syst., 2009

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals.
Microprocess. Microsystems, 2008

A matrix product accelerator for field programmable systems on chip.
Microprocess. Microsystems, 2008

2007
An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
I systems on programmable chip.
PhD thesis, 2006

An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

SAD-Based Stereo Matching Circuit for FPGAs.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Microprocessor-based FPGA implementation of SPIHT image compression subsystems.
Microprocess. Microsystems, 2005


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