Paolo Prinetto
Orcid: 0000-0003-2400-8245
According to our database1,
Paolo Prinetto
authored at least 272 papers
between 1979 and 2024.
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Bibliography
2024
2023
Proceedings of the 2023 IEEE International Conference on Design, 2023
Proceedings of the IEEE Intl Conf on Dependable, 2023
Proceedings of the 18th International Conference on Availability, Reliability and Security, 2023
2022
IEEE Access, 2022
Proceedings of the Italian Conference on Cybersecurity (ITASEC 2022), 2022
Proceedings of the Italian Conference on Cybersecurity (ITASEC 2022), 2022
Remotizing and Virtualizing Chips and Circuits for Hardware-based Capture-the-Flag Challenges.
Proceedings of the IEEE European Symposium on Security and Privacy, 2022
Proceedings of the IEEE European Test Symposium, 2022
2021
Proceedings of the Italian Conference on Cybersecurity, 2021
Proceedings of the IEEE East-West Design & Test Symposium, 2021
Proceedings of the IEEE East-West Design & Test Symposium, 2021
2020
Proceedings of the 2020 IEEE International Workshop on Metrology for Industry 4.0 & IoT, 2020
Proceedings of the Fourth Italian Conference on Cyber Security, 2020
Proceedings of the Fourth Italian Conference on Cyber Security, 2020
Proceedings of the IEEE East-West Design & Test Symposium, 2020
Proceedings of the IEEE East-West Design & Test Symposium, 2020
A FPGA-based Control-Flow Integrity Solution for Securing Bare-Metal Embedded Systems.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
2019
Design and Review of Water Management System Using Ethernet, Wi-Fi 802.11n, Modbus, and Other Communication Standards.
Wirel. Pers. Commun., 2019
IEEE Trans. Emerg. Top. Comput., 2019
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019
2018
Int. J. Embed. Syst., 2018
Securing bitstream integrity, confidentiality and authenticity in reconfigurable mobile heterogeneous systems.
Proceedings of the IEEE International Conference on Automation, 2018
2017
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017
2016
STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability.
ACM J. Emerg. Technol. Comput. Syst., 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015
SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2015
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers.
ACM Trans. Embed. Comput. Syst., 2015
SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Int. J. Hum. Comput. Interact., 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories.
ACM Trans. Archit. Code Optim., 2014
Expert Syst. Appl., 2014
A novel algorithm and hardware architecture for fast video-based shape reconstruction of space debris.
EURASIP J. Adv. Signal Process., 2014
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 9th International Design and Test Symposium, 2014
On the impact of process variability and aging on the reliability of emerging memories (Embedded tutorial).
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
On Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014
2013
Microprocess. Microsystems, 2013
Proceedings of the 2013 IEEE 10th International Conference on Ubiquitous Intelligence and Computing and 2013 IEEE 10th International Conference on Autonomic and Trusted Computing, 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
SAFE: A self adaptive frame enhancer FPGA-based IP-core for real-time space applications.
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the 8th International Design and Test Symposium, 2013
FEMIP: A high performance FPGA-based features extractor & matcher for space applications.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
Proceedings of the Eighth International Conference on Language Resources and Evaluation, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
IEEE Trans. Computers, 2011
Sci. China Inf. Sci., 2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Proceedings of the 9th East-West Design & Test Symposium, 2011
Proceedings of the Applications of Evolutionary Computation, 2011
MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Improving accessibility for deaf people: an editor for computer assisted translation through virtual avatars.
Proceedings of the 13th International ACM SIGACCESS Conference on Computers and Accessibility, 2011
2010
System reliability evaluation using concurrent multi-level simulation of structural faults.
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the Computers Helping People with Special Needs, 2010
Automated synthesis of EDACs for FLASH memories with user-selectable correction capability.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 15th European Test Symposium, 2010
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level.
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
IEEE Des. Test Comput., 2009
Proceedings of the 3rd International Conference on Pervasive Computing Technologies for Healthcare, 2009
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
Proceedings of the 2008 East-West Design & Test Symposium, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the Electronic Healthcare, First International Conference, 2008
Influence of Parasitic Capacitance Variations on 65 nm and 32 nm Predictive Technology Model SRAM Core-Cells.
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs.
IET Comput. Digit. Tech., 2007
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 15th Asian Test Symposium, 2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
System-level functional testing from UML specifications in end-of-production industrial environments.
Int. J. Softw. Tools Technol. Transf., 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 10th European Test Symposium, 2005
A GQM Based E-Learning Platform Evaluation.
Proceedings of the 11th International Conference on Distributed Multimedia Systems, 2005
2004
A Dependable Autonomic Computing Environment for Self-Testing of Complex Heterogeneous Systems.
Proceedings of the International Workshop on Test and Analysis of Component Based Systems, 2004
Test Technology TC Newsletter.
IEEE Des. Test Comput., 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
2003
Proceedings of the International Workshop on Test and Analysis of Component-Based Systems, 2003
Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures.
IEEE Commun. Mag., 2003
Designing and Testing High Dependable Memories for Aerospace Applications.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
2002
IEEE Trans. Reliab., 2002
ACM Trans. Design Autom. Electr. Syst., 2002
IEEE Des. Test Comput., 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
SEU effect analysis in an open-source router via a distributed fault injection environment.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
2000
J. Electron. Test., 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
HD<sup>2</sup>BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 5th European Test Workshop, 2000
Proceedings of the 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 2000 Design, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
1998
ACM Trans. Design Autom. Electr. Syst., 1998
Formal Methods Syst. Des., 1998
IEEE Des. Test Comput., 1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the 1998 Design, 1998
Proceedings of the 1998 Design, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits.
Proceedings of the 1997 ACM symposium on Applied Computing, 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
Proceedings of the 9th International Conference on Tools with Artificial Intelligence, 1997
A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Proceedings of the European Design and Test Conference, 1997
Proceedings of the European Design and Test Conference, 1997
A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs.
Proceedings of the European Design and Test Conference, 1997
Simulation-based verification of network protocols performance.
Proceedings of the Advances in Hardware Design and Verification, 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
1996
GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits.
Proceedings of the Parallel Problem Solving from Nature, 1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the Eigth International Conference on Tools with Artificial Intelligence, 1996
A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits.
Proceedings of the High-Performance Computing and Networking, 1996
Proceedings of the conference on European design automation, 1996
Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment.
Proceedings of the conference on European design automation, 1996
On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications.
Proceedings of the Dependable Computing, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
Self-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case Study.
Proceedings of the 1996 European Design and Test Conference, 1996
1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of the High-Performance Computing and Networking, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits.
Proceedings of the Sixth International Conference on Tools with Artificial Intelligence, 1994
An experimental analysis of the effectiveness of the circular self-test path technique.
Proceedings of the Proceedings EURO-DAC'94, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Proceedings of the Proceedings EURO-DAC'94, 1994
1993
J. Electron. Test., 1993
An efficient tool for system-level verification of behaviors and temporal properties.
Proceedings of the European Design Automation Conference 1993, 1993
Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993
Proceedings of the Correct Hardware Design and Verification Methods, 1993
1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
Proceedings of the conference on European design automation, 1992
Proceedings of the 29th Design Automation Conference, 1992
1991
Proceedings of the First Great Lakes Symposium on VLSI, 1991
Proceedings of the conference on European design automation, 1991
1990
Microprocessing and Microprogramming, 1990
Microprocessing and Microprogramming, 1990
J. Electron. Test., 1990
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990
Proceedings of the European Design Automation Conference, 1990
Proceedings of the Computer-Aided Verification, 1990
Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990
1989
Microprocess. Microsystems, 1989
Microprocessing and Microprogramming, 1989
Expressing logical and temporal conditions in simulation environments: TPDL<sup>*</sup>.
Microprocessing and Microprogramming, 1989
Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989
1988
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988
Formal Verification of Hardware Correctness: Introduction and Survey of Current Research.
Computer, 1988
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988
1986
Experiences in Prolog-Based DFT Rule Checking.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986
1985
1984
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984
1983
Proceedings of the 20th Design Automation Conference, 1983
1982
Proceedings of the 15th annual workshop on Microprogramming, 1982
1979
Proceedings of the 12th annual workshop on Microprogramming, 1979