Paolo Meloni
Orcid: 0000-0002-8106-4641
According to our database1,
Paolo Meloni
authored at least 84 papers
between 2005 and 2024.
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Bibliography
2024
Reducing False Alarms in Wearable Seizure Detection With EEGformer: A Compact Transformer Model for MCUs.
IEEE Trans. Biomed. Circuits Syst., June, 2024
A Noisy Beat is Worth 16 Words: a Tiny Transformer for Low-Power Arrhythmia Classification on Microcontrollers.
CoRR, 2024
Design of an AI-driven Architecture with Cobots for Digital Transformation to Enhance Quality Control in the Food Industry.
Proceedings of the Adjunct Proceedings of the 32nd ACM Conference on User Modeling, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the Design and Architectures for Signal and Image Processing, 2024
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024
2023
J. Signal Process. Syst., September, 2023
IEEE Access, 2023
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023
2022
An Adaptive Cognitive Sensor Node for ECG Monitoring in the Internet of Medical Things.
IEEE Access, 2022
A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA.
IEEE Access, 2022
IEEE Access, 2022
Integration of Energy Storage Systems within Modular Multilevel Converters for Medium-Voltage Distribution Networks.
Proceedings of the IECON 2022, 2022
Proceedings of the Design and Architecture for Signal and Image Processing, 2022
Proceedings of the Design and Architecture for Signal and Image Processing, 2022
EEGformer: Transformer-Based Epilepsy Detection on Raw EEG Traces for Low-Channel-Count Wearable Continuous Monitoring Devices.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022
2021
Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021).
CoRR, 2021
ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge.
IEEE Access, 2021
Proceedings of the Database and Expert Systems Applications - DEXA 2021 Workshops, 2021
2020
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge.
IEEE Embed. Syst. Lett., 2020
ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays.
IEEE Access, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A Closed-Loop System Processing High-Density Electrical Recordings and Visual Stimuli to Study Retinal Circuits Properties.
Proceedings of the 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER), 2019
Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019
Proceedings of the Cyber-Physical Systems PhD Workshop 2019, an event held within the CPS Summer School "Designing Cyber-Physical Systems, 2019
Proceedings of the Cyber-Physical Systems PhD Workshop 2019, an event held within the CPS Summer School "Designing Cyber-Physical Systems, 2019
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
2018
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs.
ACM Trans. Reconfigurable Technol. Syst., 2018
Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays.
IEEE Trans. Biomed. Circuits Syst., 2018
Architecture-aware design and implementation of CNN algorithms for embedded inference: the ALOHA project.
Proceedings of the 30th International Conference on Microelectronics, 2018
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018
2017
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy.
J. Signal Process. Syst., 2017
J. Syst. Archit., 2017
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing.
IEEE Embed. Syst. Lett., 2017
On-FPGA Real-Time Processing of Biological Signals From High-Density MEAs: a Design Space Exploration.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
Feasibility Study of Real-Time Spiking Neural Network Simulations on a Swarm Intelligence Based Digital Architecture.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
2016
J. Signal Process. Syst., 2016
Microprocess. Microsystems, 2016
Microprocess. Microsystems, 2016
Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures.
J. Electr. Comput. Eng., 2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
2014
J. Real Time Image Process., 2014
A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Online process transformation for polyhedral process networks in shared-memory MPSoCs.
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014
A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014
2013
Microprocess. Microsystems, 2013
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.
Microprocess. Microsystems, 2013
A Low Overhead Self-adaptation Technique for KPN Applications on NoC-based MPSoCs.
Proceedings of the PECCS 2013, 2013
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
Welcome to the 2013 conference on design and architectures for signal and image processing (DASIP) in Cagliari, Italy.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
2012
Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper.
VLSI Design, 2012
Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks.
VLSI Design, 2012
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011
2010
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures.
IEEE Embed. Syst. Lett., 2010
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010
2007
VLSI Design, 2007
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2007
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
2006
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Networks on Chips: A Synthesis Perspective.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005