Paolo Magnone
Orcid: 0000-0003-4117-5408
According to our database1,
Paolo Magnone
authored at least 15 papers
between 2007 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Experimental analysis of variability in WS<sub>2</sub>-based devices for hardware security.
CoRR, 2023
2020
Suppression of Second-Order Harmonic Current for Droop-Controlled Distributed Energy Resource Converters in DC Microgrids.
IEEE Trans. Ind. Electron., 2020
Performance improvement of pulse width-amplitude modulation-based quasi-Z-source inverters: Analysis and implementation.
Int. J. Circuit Theory Appl., 2020
2018
Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress.
Microelectron. Reliab., 2018
Plug and Play DC-DC Converters for Smart DC Nanogrids with Advanced Control Ancillary Services.
Proceedings of the 23rd IEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, 2018
2017
Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide.
Microelectron. Reliab., 2017
2012
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Microelectron. Reliab., 2012
2011
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
2007
Interfacial layer quality effects on low-frequency noise (1/f) in p-MOSFETs with advanced gate stacks.
Microelectron. Reliab., 2007
Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics.
Microelectron. Reliab., 2007