Paolo Madoglio

According to our database, Paolo Madoglio authored at least 16 papers between 2007 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

A Cellular Multiband DTC-Based Digital Polar Transmitter With -153-dBc/Hz Noise in 14-nm FinFET.

Paolo Madoglio, Yorgos Palaskas, Jörn Angel, Jakob M. Tomasik, Sven Hampel, Petra Schubert, Peter Preyler, Thomas Mayer, Thomas Bauernfeind, Peter Plechinger, Ashoke Ravi, Ofir Degani, Rotem Banin, Eshel Gordon, Dimo Martev, Timo Gossmann, Andreas Holm, Zdravko Boos

IEEE J. Solid State Circuits, 2020

Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS.

Parmoon Seddighrad, Yorgos Palaskas, Hongtao Xu, Paolo Madoglio, Kailash Chandrashekar, David J. Allstot

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

A Cellular Multiband DTC-Based Digital Polar Transmitter With -153 dBc/Hz Noise in 14-nm FinFET.

Yorgos Palaskas, Peter Plechinger, Ashoke Ravi, Ofir Degani, Rotem Banin, Eshel Gordon, Zdravko Boos, Paolo Madoglio, Jörn Angel, Jakob M. Tomasik, Sven Hampel, Petra Schubert, Peter Preyler, Thomas Mayer, Thomas Bauernfeind

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2017

13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications.

Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Luis Cuellar, Muhammad Faisal, Yee William Li, Hyung Seok Kim, Khoa Minh Nguyen, Yulin Tan, Brent R. Carlton, Vaibhav A. Vaidya, Yanjie Wang, Thomas Tetzlaff, Satoshi Suzuki, Amr Fahim, Parmoon Seddighrad, Jianyong Xie, Zhichao Zhang, Divya Shree Vemparala, Ashoke Ravi, Stefano Pellerano, Yorgos Palaskas

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2013

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique.

Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Dan Shi, Pin-en Su, Paolo Madoglio, Yee William Li, Ashoke Ravi

IEEE J. Solid State Circuits, 2013

2012

A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS.

Ashoke Ravi, Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre-Hernandez, Masoud Sajadieh, J. E. Zarate-Roldan, Ofir Bochobza-Degani, Hasnain Lakdawala, Yorgos Palaskas

IEEE J. Solid State Circuits, 2012

A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS.

Paolo Madoglio, Ashoke Ravi, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre, Masoud Sajadieh, Ofir B. Degani, Hasnain Lakdawala, Yorgos Palaskas

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management.

Kailash Chandrashekar, Stefano Pellerano, Paolo Madoglio, Ashoke Ravi, Yorgos Palaskas

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A digital fractional-N PLL with a 3mW 0.004mm² 6-bit PVT and mismatch insensitive TDC.

Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Pin-en Su, Paolo Madoglio, Yee William Li, Ashoke Ravi

Proceedings of the 38th European Solid-State Circuit conference, 2012

2010

Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL.

Marco Zanuso, Paolo Madoglio, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving.

Paolo Madoglio, Ashoke Ravi, Luis Cuellar, Stefano Pellerano, Parmoon Seddighrad, Ismael Lomeli, Yorgos Palaskas

IEEE J. Solid State Circuits, 2010

AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic.

Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita

EURASIP J. Embed. Syst., 2010

2009

A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS.

Stefano Pellerano, Paolo Madoglio, Yorgos Palaskas

IEEE J. Solid State Circuits, 2009

A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS.

Stefano Pellerano, Paolo Madoglio, Yorgos Palaskas

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving.

Paolo Madoglio, Ashoke Ravi, Luis Cuellar, Stefano Pellerano, Parmoon Seddighrad, Ismael Lomeli, Yorgos Palaskas

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2007

Quantization Effects in All-Digital Phase-Locked Loops.

Paolo Madoglio, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita

IEEE Trans. Circuits Syst. II Express Briefs, 2007