Paolo Burgio

Orcid: 0000-0003-1954-7201

According to our database1, Paolo Burgio authored at least 48 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
GPU implementation of the Frenet Path Planner for embedded autonomous systems: A case study in the F1tenth scenario.
J. Syst. Archit., 2024

Adaptive Localization for Autonomous Racing Vehicles with Resource-Constrained Embedded Platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

The Degree of Entanglement: Cyber-Physical Awareness in Digital Twin Applications.
Proceedings of the 21st IEEE Consumer Communications & Networking Conference, 2024

2023
Time-sensitive autonomous architectures.
Real Time Syst., December, 2023

Optimized Local Path Planner Implementation for GPU-Accelerated Embedded Systems.
IEEE Embed. Syst. Lett., December, 2023

Performance/power assessment of CNN packages on embedded automotive platforms.
CoRR, 2023

Interference analysis of shared last-level cache on embedded GP-GPUs with multiple CUDA streams.
CoRR, 2023

Enabling predictable parallelism in single-GPU systems with persistent CUDA threads.
CoRR, 2023

Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Real-Time Requirements for ADAS Platforms Featuring Shared Memory Hierarchies.
IEEE Des. Test, 2022

Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Understanding and Mitigating Memory Interference in FPGA-based HeSoCs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

An FPGA Overlay for Efficient Real-Time Localization in 1/10th Scale Autonomous Vehicles.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Performance modeling of heterogeneous HW platforms.
Microprocess. Microsystems, November, 2021

SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms.
IEEE Access, 2021

A Full-Featured, Enhanced Cost Function to Mitigate Motion Sickness in Semi- and Fully-autonomous Vehicles.
Proceedings of the 7th International Conference on Vehicle Technology and Intelligent Transport Systems, 2021


2020
An Automatic Scenario Generator for Validation of Automated Valet Parking Systems.
Proceedings of the 6th International Conference on Vehicle Technology and Intelligent Transport Systems, 2020

Real-Time clustering and LiDAR-camera fusion on embedded platforms for self-driving cars.
Proceedings of the Fourth IEEE International Conference on Robotic Computing, 2020

Human-Automation Interaction Through Shared and Traded Control Applications.
Proceedings of the Intelligent Human Systems Integration 2020, 2020

Graphic Interfaces in ADAS: from requirements to implementation.
Proceedings of the GoodTechs '20: 6th EAI International Conference on Smart Objects and Technologies for Social Good, 2020

2019
F1/10: An Open-Source Autonomous Cyber-Physical Platform.
CoRR, 2019

An open source research framework for IoT-capable smart traffic lights.
Proceedings of the 5th EAI International Conference on Smart Objects and Technologies for Social Good, 2019

System Performance Modelling of Heterogeneous HW Platforms: An Automated Driving Case Study.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019


2018
The Key Role of Memory in Next-Generation Embedded Systems for Military Applications.
Proceedings of 6th International Conference in Software Engineering for Defence Applications, 2018

Artificial Neural Networks: The Missing Link Between Curiosity and Accuracy.
Proceedings of the Intelligent Systems Design and Applications, 2018

Convolutional Neural Networks on Embedded Automotive Platforms: A Qualitative Comparison.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

2017
A software stack for next-generation automotive systems on many-core heterogeneous platforms.
Microprocess. Microsystems, 2017

Adaptive Coordination in Autonomous Driving: Motivations and Perspectives.
Proceedings of the 26th IEEE International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises, 2017

2016
Keynote 4: "Embedded platforms for next-generation autonomous driving systems".
Proceedings of the 11th International Design & Test Symposium, 2016

A Software Stack for Next-Generation Automotive Systems on Many-Core Heterogeneous Platforms.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
P-SOCRATES: A parallel software framework for time-critical many-core systems.
Microprocess. Microsystems, 2015

Efficient Implementation of Genetic Algorithms on GP-GPU with Scheduled Persistent CUDA Threads.
Proceedings of the Seventh International Symposium on Parallel Architectures, 2015

2014
A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Variation-tolerant OpenMP tasking on tightly-coupled processor clusters.
Proceedings of the Design, Automation and Test in Europe, 2013

Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters.
Proceedings of the Design, Automation and Test in Europe, 2013

Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Fast and lightweight support for nested parallelism on cluster-based embedded many-cores.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Supporting OpenMP on a multi-cluster embedded MPSoC.
Microprocess. Microsystems, 2011

Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip.
Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011

MPOpt-Cell: a high-performance data-flow programming environment for the CELL BE processor.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems.
Proceedings of the 28th International Conference on Computer Design, 2010

Evaluating OpenMP Support Costs on MPSoCs.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Vertical stealing: robust, locality-aware do-all workload distribution for 3D MPSoCs.
Proceedings of the 2010 International Conference on Compilers, 2010


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