Pao-Lung Chen

According to our database, Pao-Lung Chen authored at least 18 papers between 2005 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

A Fully Synthesizable Ultra- ${N}$ Audio Frequency Multiplier for HDMI Applications.

Pao-Lung Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019

An All-Digital Clock Generator with Modified Dynamic Frequency Counting Loop and LFSR Dithering.

Pao-Lung Chen

Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019

2017

A Reconfigurable TAF-DPS Frequency Synthesizer on FPGA Achieving 2 ppb Frequency Granularity and Two-Cycle Switching Speed.

Liming Xiu, Pao-Lung Chen

IEEE Trans. Ind. Electron., 2017

2016

An open-loop fractional divider based on direct phase synthesis.

Pao-Lung Chen

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2016

A low-cost carry look-ahead adder for flying-adder frequency synthesizer.

Pao-Lung Chen

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2016

2015

Flying-Adder Frequency Synthesizer with a Novel Counter-Based Randomization Method.

Pao-Lung Chen, Da-Chen Lee, Wei-Chia Li

IEICE Trans. Electron., 2015

Digitally controlled oscillator with storage based randomization for spurs reduction.

Pao-Lung Chen, Ting-Yao Chen

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015

Carry randomization with fractional control of a De Bruijn sequence.

Pao-Lung Chen

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015

2013

A jumping algorithm for calibration in multiphase delay locked loop.

Pao-Lung Chen

Proceedings of the 10th IEEE International Conference on Control and Automation, 2013

2011

An Interpolated Flying-Adder-Based Frequency Synthesizer.

Pao-Lung Chen, Chun-Chien Tsai

J. Electr. Comput. Eng., 2011

Simulation-Based Analysis and Experimental Verification of Chaotic Circuits.

Pao-Lung Chen, Ke-Xin Lin

Proceedings of the Next Wave in Robotics - 14th FIRA RoboWorld Congress, 2011

2010

Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator.

Pao-Lung Chen

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A multiphase all-digital delay-locked loop with reuse SAR.

Pao-Lung Chen, Tzu-Siang Wang, Jyun-Han Ciou

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2008

Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop.

Pao-Lung Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2006

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications.

Pao-Lung Chen, Ching-Che Chung, Jyh-Neng Yang, Chen-Yi Lee

IEEE J. Solid State Circuits, 2006

2005

A portable digitally controlled oscillator using novel varactors.

Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee

IEEE Trans. Circuits Syst. II Express Briefs, 2005

A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting.

Pao-Lung Chen, Chen-Yi Lee

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications.

Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005