Pao-Cheng Chiu
According to our database1,
Pao-Cheng Chiu
authored at least 8 papers
between 2009 and 2019.
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Bibliography
2019
An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2016
A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters.
IEEE J. Solid State Circuits, 2016
2015
A 16nm FinFet 19/39MHz 78/72dB DR noise-injected aggregated CTSDM ADC for configurable LTE advanced CCA/NCCA Application.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
A 960MS/s DAC with 80dB SFDR in 20nm CMOS for multi-mode baseband wireless transmitter.
Proceedings of the Symposium on VLSI Circuits, 2014
2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009