Paniz Foroutan

According to our database, Paniz Foroutan authored at least 3 papers between 2014 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

An improved scheme for pre-computed patterns in core-based SoC architecture.

Elaheh Sadredini, Reza Rahimi, Paniz Foroutan, Mahmood Fathy, Zainalabedin Navabi

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2014

A mathematical model for estimating acceptable ratio of test patterns.

Vahid Janfaza, Paniz Foroutan, Bahjat Forouzandeh, M. H. Haghbayan

Proceedings of the 2014 East-West Design & Test Symposium, 2014

A heuristic path selection method for small delay defects test.

Paniz Foroutan, Mehdi Kamal, Zainalabedin Navabi

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014