Pang-Yen Lou
According to our database1,
Pang-Yen Lou
authored at least 10 papers
between 2017 and 2024.
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Collaborative distances:
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Bibliography
2024
Microelectron. J., 2024
2023
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process.
Integr., May, 2023
2021
Microelectron. J., 2021
Circuits Syst. Signal Process., 2021
2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process.
Circuits Syst. Signal Process., 2021
Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer.
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
2019
74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Proceedings of the IEEE International Conference on Consumer Electronics, 2019
2017
Proceedings of the IEEE International Conference on Consumer Electronics, 2017