Panagiotis Sakellariou

Orcid: 0000-0002-6481-1844

According to our database1, Panagiotis Sakellariou authored at least 6 papers between 2012 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Reconfigurable RO-Path Delay Sensor.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

2016
Application-Specific Low-Power Multipliers.
IEEE Trans. Computers, 2016

2012
An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Low-Power Delay Sensors on FPGAs.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Low-power two's-complement multiplication based on selective activation.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012


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