Pallavi Paliwal

According to our database, Pallavi Paliwal authored at least 10 papers between 2012 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Stability Analysis for Fast Settling Switched Digital Phase-Locked Loops (DPLLs).

Zeeshan Ali, Pallavi Paliwal, Phani Raj, Deepak Anand, Debasattam Pal, Shalabh Gupta

IEEE Control. Syst. Lett., 2023

2022

A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM.

Zeeshan Ali, Pallavi Paliwal, Rupesh Lad, Dhanraj Bhukya, Shalabh Gupta

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2020

A Fast Settling Fractional-N DPLL With Loop-Order Switching.

Pallavi Paliwal, Vivek Yadav, Zeeshan Ali, Shalabh Gupta

IEEE Trans. Very Large Scale Integr. Syst., 2020

2019

A High-Resolution Digital Phase Interpolator Based CDR with a Half-Rate Hybrid Phase Detector.

Arun Goyal, Souvik Ghosh, Sandeep Goyal, Pallavi Paliwal, Shalabh Gupta

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Stability Analysis for Fast Settling Switched DPLL.

Pallavi Paliwal, Debasattam Pal, Shalabh Gupta

CoRR, 2018

2016

A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop.

Pallavi Paliwal, Jaydip Fadadu, Anil Chawda, Shalabh Gupta

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A low-jitter digital-to-time converter with look-ahead multi-phase DDS.

Harishankar Sahu, Pallavi Paliwal, Vivek Yadav, Shalabh Gupta

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2014

High resolution digital-to-time converter for low jitter digital PLLs.

Anil Chawda, Pallavi Paliwal, Priyank Laad, Shalabh Gupta

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

Tradeoffs between settling time and jitter in phase locked loops.

Pallavi Paliwal, Priyank Laad, Mohanrao Sattineni, Shalabh Gupta

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012

Circuit Optimization at 22nm Technology Node.

Angada B. Sachid, Pallavi Paliwal, S. Joshi, Maryam Shojaei Baghini, Dinesh Sharma, V. Ramgopal Rao

Proceedings of the 25th International Conference on VLSI Design, 2012