Pallabi Sarkar

According to our database, Pallabi Sarkar authored at least 15 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

System Complexity Reduction Using 3-D Matrices and Novel Logic Gates.

Nameshwari Verma, Pallabi Sarkar

Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

2020

Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography.

Mahendra Rathor, Pallabi Sarkar, Vipul Kumar Mishra, Anirban Sengupta

Proceedings of the 10th IEEE International Conference on Consumer Electronics, 2020

2019

Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters].

Pallabi Sarkar, Dipanjan Roy, Anirban Sengupta, Mrinal Kanti Naskar

IEEE Consumer Electron. Mag., 2019

2018

Optimizing DSP Cores Using Design Transformation [Hardware Matters].

Dipanjan Roy, Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar

IEEE Consumer Electron. Mag., 2018

Obfuscation of Fault Secured DSP Design Through Hybrid Transformation.

Anirban Sengupta, Shubha Neema, Pallabi Sarkar, Sri Harsha P, Saraju P. Mohanty, Mrinal Kanti Naskar

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

Designing Low-Cost Hardware Accelerators for CE Devices [Hardware Matters].

Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar

IEEE Consumer Electron. Mag., 2017

A Firefly Algorithm Driven Approach for High Level Synthesis.

Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2015

GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis.

Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar

Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015

2013

A multi parametric optimization based novel approach for an efficient design space exploration for ASIC design.

Tulasi Krishna, Priyam Sachdeva, Suraj Kumar Dhanuka, Mohit Gagrani, Pallabi Sarkar

Proceedings of the International Conference on Advances in Computing, 2013

2012

A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels.

Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar

Swarm Evol. Comput., 2012

Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design.

Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar

Microprocess. Microsystems, 2012

2011

Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis.

Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal

Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications.

Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal

Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

Integrated design space exploration based on power-performance trade-off using genetic algorithm.

Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar

Proceedings of the International Conference on Advances in Computing and Artificial Intelligence, 2011

Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis.

Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta

Proceedings of the International Conference on Advances in Computing and Artificial Intelligence, 2011