Pallab Kumar Nath
Orcid: 0000-0003-0570-8430
According to our database1,
Pallab Kumar Nath
authored at least 9 papers
between 2016 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
2021
Corrigendum to High throughput unified architecture of LEA algorithm for image encryption' Microprocessors and Microsystems Vol 78 (2020) 1-10
Microprocess. Microsystems, September, 2021
2020
IEEE Trans. Instrum. Meas., 2020
Microprocess. Microsystems, 2020
A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process.
Integr., 2020
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
2016
A high speed, memory efficient line based VLSI architecture for the dual mode inverse discrete wavelet transform of JPEG2000 decoder.
Microprocess. Microsystems, 2016