Pallab Dasgupta
Orcid: 0000-0002-2178-8154
According to our database1,
Pallab Dasgupta
authored at least 226 papers
between 1994 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Efficient Low-Memory Implementation of Sparse CNNs Using Encoded Partitioned Hybrid Sparse Format.
ACM Trans. Embed. Comput. Syst., November, 2024
Towards Adaptive IMFs - Generalization of utility functions in Multi-Agent Frameworks.
CoRR, 2024
Proceedings of the 10th IEEE International Conference on Network Softwarization, 2024
An Adaptive Interpretable Safe-RL Approach for Addressing Smart Grid Supply-Side Uncertainties.
Proceedings of the Explainable and Transparent AI and Multi-Agent Systems, 2024
PURSE: Property Ordering Using Runtime Statistics for Efficient Multi - Property Verification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 23rd International Conference on Autonomous Agents and Multiagent Systems, 2024
Proceedings of the 23rd International Conference on Autonomous Agents and Multiagent Systems, 2024
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024
2023
Comput. Vis. Image Underst., October, 2023
J. Cryptol., July, 2023
Safe and Stable RL (S<sup>2</sup>RL) Driving Policies Using Control Barrier and Control Lyapunov Functions.
IEEE Trans. Intell. Veh., February, 2023
CoVerPlan: A Comprehensive Verification Planning Framework Leveraging PSS Specifications.
ACM Trans. Design Autom. Electr. Syst., January, 2023
Accelerating Defect Simulation in Analog and Mixed-Signal Circuits by Parallel Defect Injection.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
Proceedings of the IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, 2023
Domain Adaptation of Reinforcement Learning Agents based on Network Service Proximity.
Proceedings of the 9th IEEE International Conference on Network Softwarization, 2023
Proceedings of the International Joint Conference on Neural Networks, 2023
Proceedings of the Explainable and Transparent AI and Multi-Agent Systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 2023 International Conference on Autonomous Agents and Multiagent Systems, 2023
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023
Proceedings of the Workshop on Artificial Intelligence Safety 2023 (SafeAI 2023) co-located with the Thirty-Seventh AAAI Conference on Artificial Intelligence (AAAI 2023), 2023
2022
IEEE Trans. Netw. Serv. Manag., December, 2022
IEEE Trans. Intell. Transp. Syst., 2022
The CoveRT Approach for Coverage Management in Analog and Mixed-Signal Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
Proceedings of the PRICAI 2023: Trends in Artificial Intelligence, 2022
Proceedings of the IEEE PES Innovative Smart Grid Technologies - Asia, 2022
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022
2021
ACM Trans. Design Autom. Electr. Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Semi-lexical languages: a formal basis for using domain knowledge to resolve ambiguities in deep-learning based computer vision.
Pattern Recognit. Lett., 2021
J. Artif. Intell. Res., 2021
IEEE Embed. Syst. Lett., 2021
IEEE Embed. Syst. Lett., 2021
Circuits Syst. Signal Process., 2021
Circuits Syst. Signal Process., 2021
Methodology for Biasing Random Simulation for Rapid Coverage of Corner Cases in AMS Designs.
CoRR, 2021
Quantitative Corner Case Feature Analysis of Hybrid Automata with ForFET<sup>SMT</sup>.
CoRR, 2021
An RL based Approach for Thermal-Aware Energy Optimized Task Scheduling in Multi-core Processors.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
Proceedings of the 2021 IEEE PES Innovative Smart Grid Technologies, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
ACM Trans. Design Autom. Electr. Syst., 2020
ACM Trans. Embed. Comput. Syst., 2020
Robust <i>f</i><sub>0</sub> extraction from monophonic signals using adaptive sub-band filtering.
Speech Commun., 2020
IET Comput. Digit. Tech., 2020
IACR Cryptol. ePrint Arch., 2020
A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits.
J. Electron. Test., 2020
Early-Stage Resource Estimation from Functional Reliability Specification in Embedded Cyber-Physical Systems.
CoRR, 2020
Semi-Lexical Languages - A Formal Basis for Unifying Machine Learning and Symbolic Reasoning in Computer Vision.
CoRR, 2020
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Proceedings of the Workshop on Artificial Intelligence Safety 2020 co-located with the 29th International Joint Conference on Artificial Intelligence and the 17th Pacific Rim International Conference on Artificial Intelligence (IJCAI-PRICAI 2020), 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
IEEE Trans. Inf. Forensics Secur., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
J. Cryptogr. Eng., 2019
Performance and energy aware robust specification of control execution patterns under dropped samples.
IET Comput. Digit. Tech., 2019
Synthesizing Performance-Aware (m, k)-Firm Control Execution Patterns Under Dropped Samples.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Identification of Test Cases for Automated Driving Systems Using Bayesian Optimization.
Proceedings of the 2019 IEEE Intelligent Transportation Systems Conference, 2019
Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits.
Proceedings of the 28th IEEE Asian Test Symposium, 2019
2018
ExpFault: An Automated Framework for Exploitable Fault Characterization in Block Ciphers.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Embed. Syst. Lett., 2018
Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018
Proceedings of the Heritage Preservation - A Computational Approach, 2018
2017
Formal Methods for Validation and Test Point Prioritization in Railway Signaling Logic.
IEEE Trans. Intell. Transp. Syst., 2017
ACM Trans. Embed. Comput. Syst., 2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Feature Based Identification of Transmission Line Faults by Synchronous Monitoring of PMUs.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
An Automated Framework for Exploitable Fault Identification in Block Ciphers - A Data Mining Approach.
Proceedings of the PROOFS 2017, 2017
Proceedings of the Automated Technology for Verification and Analysis, 2017
2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
J. Appl. Log., 2016
IEEE Embed. Syst. Lett., 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016
A Robust Non-Parametric and Filtering Based Approach for Glottal Closure Instant Detection.
Proceedings of the 17th Annual Conference of the International Speech Communication Association, 2016
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2016
2015
J. Autom. Reason., 2015
IEEE Des. Test, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 2015 International Conference on Advances in Computing, 2015
A New Approach for Minimal Environment Construction for Modular Property Verification.
Proceedings of the 24th IEEE Asian Test Symposium, 2015
Proceedings of the 2015 Asia-Pacific Software Engineering Conference, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Time-budgeting: a component based development methodology for real-time embedded systems.
Formal Aspects Comput., 2014
Proceedings of the 2014 IEEE International Conference on Control System, 2014
Acceptance and random generation of event sequences under real time calculus constraints.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Embedded Systems Development, From Functional Models to Implementations, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
An Integrated Approach for Fine-Grained Power and Peak Temperature Management During High-Level Synthesis.
J. Low Power Electron., 2013
Integr., 2013
IEEE Embed. Syst. Lett., 2013
Formal Methods for Early Analysis of Functional Reliability in Component-Based Embedded Applications.
IEEE Embed. Syst. Lett., 2013
A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture
CoRR, 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the Pattern Recognition and Machine Intelligence, 2013
Model checking of global power management strategies in software with temporal logic properties.
Proceedings of the 6th India Software Engineering Conference, 2013
Proceedings of the 6th India Software Engineering Conference, 2013
Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures : Extended Abstract.
Proceedings of the IJCAI 2013, 2013
Handling fault detection latencies in automata-based scheduling for embedded control software.
Proceedings of the 2013 IEEE International Symposium on Computer-Aided Control System Design, 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults.
ACM Trans. Design Autom. Electr. Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
ACM SIGSOFT Softw. Eng. Notes, 2012
J. Low Power Electron., 2012
J. Artif. Intell. Res., 2012
IET Comput. Digit. Tech., 2012
J. Electron. Test., 2012
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the Fifth Annual Symposium on Combinatorial Search, 2012
Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework.
Proceedings of the International Symposium on Electronic System Design, 2012
Reliability annotations to formal specifications of context-sensitive safety properties in embedded systems.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the AI 2012: Advances in Artificial Intelligence, 2012
Proceedings of the AI 2012: Advances in Artificial Intelligence, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Formal methods for coverage analysis of architectural power states in power-managed designs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS Architecture.
Proceedings of the Advances in Computing and Information Technology - Proceedings of the Second International Conference on Advances in Computing and Information Technology (ACITY) July 13-15, 2012, Chennai, India, 2012
2011
Chassis: A Platform for Verifying PMU Integration Using Autogenerated Behavioral Models.
ACM Trans. Design Autom. Electr. Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Secur. Commun. Networks, 2011
Auxiliary State Machines and Auxiliary Functions: Constructs for Extending AMS Assertions.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Proceedings of the International Symposium on Electronic System Design, 2011
Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
IEEE Trans. Netw. Serv. Manag., 2010
Microelectron. J., 2010
A static verification approach for architectural integration of mixed-signal integrated circuits.
Integr., 2010
Integrated security analysis framework for an enterprise network - a formal approach.
IET Inf. Secur., 2010
CoRR, 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
A Spatio-Temporal Role-Based Access Control Model for Wireless LAN Security Policy Management.
Proceedings of the Information Systems, Technology and Management, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the Recent Trends in Network Security and Applications, 2010
A SAT Based Verification Framework for Wireless LAN Security Policy Management Supported by STRBAC Model.
Proceedings of the Recent Trends in Network Security and Applications, 2010
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010
2009
ACM Trans. Design Autom. Electr. Syst., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the First International Conference on Networks and Communications, 2009
Proceedings of the Information Systems Security, 5th International Conference, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
ACM Trans. Design Autom. Electr. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the Automated Technology for Verification and Analysis, 2008
2007
ACM Trans. Design Autom. Electr. Syst., 2007
BUSpec: A framework for generation of verification aids for standard bus protocol specifications.
Integr., 2007
IET Comput. Digit. Tech., 2007
IET Circuits Devices Syst., 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
The open family of temporal logics: Annotating temporal operators with input constraints.
ACM Trans. Design Autom. Electr. Syst., 2005
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
SAT based solutions for consistency problems in formal property specifications for open systems.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
2004
The power of first-order quantification over states in branching and linear time temporal logics.
Inf. Process. Lett., 2004
Property Refinement Techniques for Enhancing Coverage of Formal Property Verification.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
The BUSpec platform for automated generation of verification aids for standard bus protocols.
Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004
Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures.
Proceedings of the Distributed Computing, 2004
Formal verification coverage: computing the coverage gap between temporal specifications.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?
Proceedings of the 2004 Design, 2004
2003
J. Autom. Reason., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
Solving Constraint Optimization Problems from CLP-Style Specifications Using Heuristic Search Techniques.
IEEE Trans. Knowl. Data Eng., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Abstraction of word-level linear arithmetic functions from bit-level component descriptions.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
1999
An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Adaptive Algorithms for Scheduling Static Task Graphs in Dynamic Distributed Systems.
Proceedings of the High Performance Computing, 1999
Multiobjective heuristic search - an introduction to intelligent search methods for multicriteria optimization.
Computational intelligence, Vieweg, ISBN: 978-3-528-05708-4, 1999
1998
A Heuristic for the Maximum Processor Requirement for Scheduling Layered Task Graphs with Coloring.
J. Parallel Distributed Comput., 1998
1997
1996
Inf. Process. Lett., 1996
Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1996
1995
A Correction to "Agent Searching in a Tree and the Optimality of Iterative Deepening".
Artif. Intell., 1995
A Near Optimal Algorithm for the Extended Cow-Path Problem in the Presence of Relative Errors.
Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1995
1994
Artif. Intell., 1994
Proceedings of the Seventh International Conference on VLSI Design, 1994