Palkesh Jain

Orcid: 0000-0002-7758-6834

According to our database1, Palkesh Jain authored at least 18 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks.
ACM Trans. Design Autom. Electr. Syst., January, 2023

2021
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2019
NanoTherm: An Analytical Fourier-Boltzmann Framework for Full Chip Thermal Simulations.
Proceedings of the International Conference on Computer-Aided Design, 2019

2017
Algorithms and methodologies for interconnect reliability analysis of integrated circuits.
PhD thesis, 2017

Fast Stochastic Analysis of Electromigration in Power Distribution Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015
Reducing the signal Electromigration effects on different logic gates by cell layout optimization.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Stochastic and topologically aware electromigration analysis for clock skew.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Impact on performance, power, area and wirelength using electromigration-aware cells.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A retargetable and accurate methodology for logic-IP-internal electromigration assessment.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Asymmetric Aging: Introduction and Solution for Power-Managed Mixed-Signal SoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Design-in-reliability: From library modeling and optimization to gate-level verification.
Microelectron. Reliab., 2014

A systematic approach for analyzing and optimizing cell-internal signal electromigration.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2012
Accurate Current Estimation for Interconnect Reliability Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2011
Accurate Estimation of Signal Currents for Reliability Analysis Considering Advanced Waveform-Shape Effects.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

2006
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006


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