Palak Yash

According to our database1, Palak Yash authored at least 2 papers between 2021 and 2022.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of six.

Timeline

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Links

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Bibliography

2022
Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGA.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

2021
Efficient Hardware Implementation of Cube Architecture using Yavadunam Sutra on FPGA.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021


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