Pai-Yu Chen
Orcid: 0000-0002-9146-2192
According to our database1,
Pai-Yu Chen
authored at least 25 papers
between 2014 and 2019.
Collaborative distances:
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Bibliography
2019
IEEE Des. Test, 2019
2018
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Reliability perspective of resistive synaptic devices on the neuromorphic system performance.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Multi Scale Comput. Syst., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Exploiting resistive cross-point array for compact design of physical unclonable function.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
Proceedings of the 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014