Padmaja Bhamidipati

According to our database, Padmaja Bhamidipati authored at least 7 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

NoC-Armor: Leveraging Quantitative Analysis for Enhanced Security.

Padmaja Bhamidipati, Ranga Vemuri

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

QA-NoCs: Quantitative Analysis for Trojan Detection in Network-on-Chips.

Padmaja Bhamidipati, Ranga Vemuri

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2023

ASPIRE: An Intermediate Representation for Abstract Security Policies.

Padmaja Bhamidipati, Ranga Vemuri

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2022

HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip Architecture.

Padmaja Bhamidipati, Avinash Karanth

IEEE Trans. Emerg. Top. Comput., 2022

2021

Security Analysis of a System-on-Chip Using Assertion-Based Verification.

Padmaja Bhamidipati, Shanmukha Murali Achyutha, Ranga Vemuri

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip.

Subashree Raja, Padmaja Bhamidipati, Xiaobang Liu, Ranga Vemuri

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2018

RETUNES: Reliable and Energy-Efficient Network-on-Chip Architecture.

Padmaja Bhamidipati, Avinash Karanth

Proceedings of the 36th IEEE International Conference on Computer Design, 2018