Pablo Viana

According to our database, Pablo Viana authored at least 8 papers between 2003 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2014

Minimum Effort Design Space Subsetting for Configurable Caches.

Mohamad Hammam Alsafrjalani, Ann Gordon-Ross, Pablo Viana

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2008

A table-based method for single-pass cache optimization.

Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass.

André Silva, Guilherme Álvaro R. M. Esmeraldo, Edna Barros, Pablo Viana

Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

A one-shot configurable-cache tuner for improved energy and performance.

Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption.

Abel Guilhermino Silva-Filho, Pablo Viana, Edna Barros, Manoel Eusébio de Lima

Proceedings of the 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 2006

Configurable cache subsetting for fast cache tuning.

Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid

Proceedings of the 43rd Design Automation Conference, 2006

2004

Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology.

Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo

Proceedings of the 2004 Design, 2004

2003

Exploring Memory Hierarchy with ArchC.

Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo

Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 2003